Graded Junction HV MOSFET Alignment and Field Control
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Solution Overview
Problem
High voltage (HV) metal oxide semiconductor (MOS) devices face limitations due to hot carrier impact ionization and alignment issues caused by undesirable steps at well edges in the silicon substrate, which restrict the voltage range and effectiveness of drain engineering in existing fabrication methods.
Innovation Solution
The method involves forming multiple well implants with different doping levels in a P-substrate, using a zero layer with an alignment target outside active device areas, and adjusting the lengths of lightly and heavily doped N-wells to create a graded junction under the field oxide, allowing for precise alignment and reduced high field effects, enabling a pseudo lightly doped drain (Ldd) structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If typical lightly doped drain (Ldd) implants are used in HV MOS devices, then the drain structure is formed, but the implants are not useful in drain engineering as the drain is under the field oxide and hot carrier impact ionization limits the voltage range
Solution Approach 1:
The patent segments the drain region into multiple distinct zones: a first doped well region with lower doping concentration and a second doped well region with higher doping concentration. This segmentation allows each region to serve different functions - the first region for high voltage operation and the second region for improved carrier transport, thereby resolving the contradiction between reliability and adaptability across voltage ranges.
Solution Approach 2:
The patent applies local quality by creating spatially varying doping concentrations within the drain region. The first doped well region has a specific doping concentration optimized for high voltage operation, while the second doped well region has a different doping concentration optimized for carrier transport. This local differentiation enables the structure to simultaneously achieve reliability at high voltages and improved performance in specific operational modes.
2Ease of manufacture
If prior technology self aligned well structures are used, then well implants are created, but undesirable steps (change in elevation) are created at the well edges in the silicon substrate surface causing alignment issues for successive well implants
Solution Approach 1:
The patent employs a preliminary action by forming a sacrificial oxide layer before the well implantation process. This oxide layer serves as a protective mask that prevents unwanted doping at critical interfaces. After implantation, the oxide is selectively removed to reveal precise alignment features without creating elevation steps, thereby maintaining both ease of manufacture and manufacturing precision.
Solution Approach 2:
The patent introduces an intermediary oxide layer that mediates between the implantation process and the substrate. This intermediary layer allows the implant to be performed without direct contact between the ion beam and the substrate surface, preventing step formation. The oxide is subsequently removed to reveal clean, step-free interfaces that facilitate precise alignment for successive implants.
3Reliability
If multiple well implants with different doping levels are formed to create graded junction, then high field effects are reduced, but the fabrication process complexity increases
Solution Approach 1:
The patent achieves multi-functionality by using the same basic implantation and oxidation process sequence for both the first and second doped well regions. The process parameters (doping concentrations, oxide thicknesses, etch patterns) are optimized to simultaneously create the graded junction structure and reduce high field effects. This universal approach reduces fabrication complexity while achieving multiple reliability improvements.
Solution Approach 2:
The patent systematically changes key process parameters - specifically the doping concentrations of the two well regions and the thickness of the sacrificial oxide layer - to optimize the graded junction profile. By carefully controlling these parameters, the patent achieves effective high field reduction while keeping the process sequence relatively simple and manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy of well implant alignment, reduces high field effects, improves drive current, eliminates hot carrier impacts, and expands the voltage range of the HV MOS device operation.
Implementation Method 1
forming a lightly doped N-well in a portion of the P-substrate by implant; forming a doped N-well in a portion of the lightly doped N-well by implant
Data Source
Figure 1(a)~1(c)
Figure 2(a)~2(d)
Figure 2A~2A(h)
AI summary
At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.