Graded Lateral Doping in Power MOSFETs
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Solution Overview
Problem
Power MOSFETs face premature failure due to breakdown of the gate dielectric layer, particularly at high electric fields, which is exacerbated by damage from ion implantation and etching processes, leading to lower quality dielectric with increased semiconductor lattice damage induced defects.
Innovation Solution
The semiconductor device design includes a source/drain region with varying dopant concentrations and a gate dielectric layer structure that spaces potentially damaged areas away from the channel region, maintaining a high-quality gate dielectric layer by ensuring uniform thickness and reduced defect concentration, thereby reducing premature failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If ion implantation and etching processes are used to fabricate the device, then the source/drain regions can be formed with appropriate doping, but the gate dielectric layer suffers damage and develops defects that reduce its quality and increase premature failure
Solution Approach 1:
The source/drain region is divided into two distinct portions: a first portion with higher dopant concentration and a second portion with lower dopant concentration. This segmentation allows the high-dose implantation to be localized away from the gate dielectric interface, preventing damage to the gate dielectric while still achieving the required doping in the source/drain regions
Solution Approach 2:
Different portions of the source/drain region are given different dopant concentrations tailored to their specific functional requirements. The first portion (farther from gate) has higher doping for current conduction, while the second portion (closer to gate) has lower doping to minimize damage to the gate dielectric layer
2Power
If high dopant concentration is used in the source/drain region to support high current density, then the device can handle high power, but the gate dielectric layer experiences increased stress and breakdown risk
Solution Approach 1:
The source/drain region is segmented into a first portion with high dopant concentration for current conduction and a second portion with low dopant concentration adjacent to the gate dielectric, allowing high power handling without compromising gate dielectric reliability
Solution Approach 2:
The dopant concentration is locally optimized: high concentration in the first portion for power handling, low concentration in the second portion for gate dielectric protection, achieving both high power capability and reliability
3Speed
If the gate dielectric layer is made thinner to reduce gate capacitance and improve switching speed, then switching performance improves, but the layer becomes more susceptible to damage from ion implantation and etching
Solution Approach 1:
The source/drain regions are formed with a graded doping structure before the gate dielectric is fully processed, ensuring that subsequent ion implantation steps do not damage the gate dielectric. This preliminary structuring protects the thin gate dielectric from harmful effects
Solution Approach 2:
By segmenting the source/drain doping into two portions, the patent enables thin gate dielectric formation without compromising integrity, as the low-dose second portion minimizes stress on the thin gate dielectric during and after fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the breakdown voltage and reliability of power MOSFETs by minimizing damage-induced defects in the gate dielectric layer, leading to improved performance and extended device lifetime.
Implementation Method 1
damage from ion implantation and etching processes, leading to lower quality dielectric with increased semiconductor lattice damage induced defects
Data Source
AI summary
A semiconductor device includes a semiconductor layer structure comprising a source/drain region, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer. The source/drain region comprises a first portion comprising a first dopant concentration and a second portion comprising a second dopant concentration. The second portion is closer to a center of the gate electrode than the first portion.