Graded Memory Segments for Power Leakage Reduction
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Solution Overview
Problem
Current mobile systems face power leakage and consumption issues due to conventional design schemes, and existing memory approaches are not optimized for multi-core processor implementations, leading to inefficient power management and long transition times between sleep and wake modes.
Innovation Solution
A memory configuration on a chip with multiple memory segments of different grades, each with a separate power supply and/or controller, allowing for adjustable voltage and performance optimization through a through-silicon via configuration and independent voltage supplies for optimal power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a single memory device with fixed power supply is used, then manufacturing is simple, but power leakage and consumption are high
Solution Approach 1:
The memory device is divided into multiple independently controllable memory segments (first memory segment, second memory segment, etc.), each with its own power supply control. This allows selective powering on/off of individual segments to reduce overall power leakage while maintaining the ability to access needed memory portions.
Solution Approach 2:
The power supply to each memory segment is made dynamic and adjustable rather than fixed. Each segment can be independently powered up or down based on operational needs, enabling the system to adapt power consumption to actual usage patterns and reduce unnecessary power leakage.
2Use of energy by moving object
If conventional memory design is used, then design is simple, but power management efficiency is poor for multi-core processors
Solution Approach 1:
The memory architecture is segmented into multiple independent memory segments, each with its own controller and power supply. This enables fine-grained power management where individual segments can be activated or deactivated based on the specific needs of different processor cores, significantly improving power management efficiency for multi-core systems.
Solution Approach 2:
Different memory segments can be configured with different power management characteristics and performance levels. Each segment can be optimized locally for specific purposes (e.g., high-speed caching for performance-critical operations, lower-power storage for less frequent access), allowing tailored power management for different functional requirements within the same memory device.
3Loss of energy
If sleep mode is implemented in standard memory, then power consumption is reduced, but transition time between sleep and wake modes is extensive
Solution Approach 1:
The memory device is divided into multiple segments that can be independently controlled. When entering a low-power state, only the unused segments need to be powered down while critical segments remain active. This selective approach dramatically reduces the transition time from sleep to wake mode compared to powering down the entire memory device, while still achieving significant power consumption reduction.
Solution Approach 2:
The power state of each memory segment can be dynamically adjusted based on real-time system needs. Rather than forcing the entire memory into a uniform sleep state, the system can maintain partial operation in critical segments, enabling faster wake-up transitions when needed while minimizing overall power consumption during idle periods.
Data Source
AI summary
Embodiments of the present invention provide a memory configuration on a chip containing multiple memory segments having different memory grades. In a typical embodiment, a single chip will be provided on which the memory segments are positioned. A memory grade may include low performance (low leakage), medium performance (medium leakage), and high performance (high leakage). Each memory segment or group of memory segments may have a separate power supply and/or controller. In one example, memory segments may be stacked in a through-silicon via configuration.