Graded Memory Stack Resistances for Uniform Voltage Distribution
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Solution Overview
Problem
Memory devices in a memory array exhibit uneven performance due to variations in effective resistance, leading to non-uniform evolution and reduced operating life, as well as inconsistent current delivery across the memory layer, caused by differences in electrical distance and access path resistance.
Innovation Solution
The memory layer is constructed with graded memory stack resistances by selectively adjusting the internal access and standalone resistances of memory devices based on their electrical distance or physical location, using techniques such as removing resistive materials, adding less conductive electrode layers, or treating layers with plasma to achieve uniform voltage distribution and improved current delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory devices are distributed across a memory layer with uniform structure, then manufacturing is simplified, but performance becomes non-uniform due to variations in electrical distance and access path resistance
Solution Approach 1:
The patent applies local quality by introducing graded memory stack resistances at different spatial locations within the memory layer. Memory stacks are configured with progressively increasing resistance values based on their position, typically from a first region to a second region. This local differentiation compensates for variations in electrical distance and access path resistance, ensuring uniform voltage distribution and consistent performance across all memory devices while maintaining a relatively simple overall manufacturing process.
Solution Approach 2:
The patent implements parameter changes by systematically varying the resistance parameter of memory stacks across the memory layer. Instead of maintaining uniform resistance values, the resistance is adjusted as a function of position, creating a graded profile. This parameter variation compensates for the non-uniform electrical characteristics inherent in distributed memory architectures, achieving performance uniformity without fundamentally changing the manufacturing approach.
2Stability of the object's composition
If memory stacks have uniform resistance values, then device consistency is improved, but voltage distribution becomes non-uniform leading to reduced operating life
Solution Approach 1:
The patent resolves this contradiction by making resistance values location-dependent rather than uniform. Memory stacks in different regions are assigned different resistance values that correspond to their electrical distance from access lines. This local quality adjustment ensures that voltage distribution becomes uniform across the memory layer, preventing premature degradation in any specific region and thereby extending the overall operating life while maintaining device consistency through controlled variation.
Solution Approach 2:
The patent applies preliminary anti-action by pre-compensating for the non-uniform voltage distribution that would otherwise occur during operation. By intentionally introducing graded resistance values during manufacturing, the design anticipates and counteracts the voltage drops that would naturally occur due to electrical distance variations. This preliminary adjustment prevents the harmful effects of non-uniform stress distribution before they can cause degradation, thereby extending operating life.
3Productivity
If access path resistance is reduced for all memory devices, then current delivery is improved, but voltage spikes become more severe affecting devices closer to access lines
Solution Approach 1:
The patent applies local quality by differentiating resistance values based on spatial location. Memory stacks closer to access lines are assigned higher resistance values, while those farther away have lower resistance values. This creates a balanced system where current delivery is maintained across all devices without concentrating excessive voltage stress on any particular group, effectively distributing the electrical stress uniformly and preventing severe voltage spikes while preserving productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniform evolution of memory devices, increases operating life, and improves current delivery metrics by evenly distributing the effects of voltage spikes across the memory layer, ensuring consistent performance and extended lifespan.
Implementation Method 1
treating layers with plasma to achieve uniform voltage distribution and improved current delivery
Data Source
AI summary
Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.