Low Voltage ESD Device Using Graded P-Region
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Solution Overview
Problem
Existing ESD devices struggle to protect low voltage integrated circuits from damage by failing to turn on quickly enough, resulting in high leakage current and increased capacitance, making it difficult to achieve low reverse breakdown voltage and effective ESD protection.
Innovation Solution
The use of zener diodes with positive and negative trigger voltages and a linearly graded P-region in ESD devices, which quickly turn on a transistor by injecting current through a P+ sidewall or field implant, providing a low impedance path for ESD events and controlling trigger and clamping voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a p-n junction Zener diode with heavily doped N and P regions is used to achieve 5 volts or less breakdown, then the reverse breakdown voltage is reduced, but the leakage current increases extremely due to electron tunneling current across the P+/N+ junction
Solution Approach 1:
The patent applies parameter changes by modifying the doping concentration profile of the P-region from uniform to linearly graded, transitioning from a constant doping concentration to a varying profile where doping concentration changes linearly from the N-junction interface toward the other junction. This parameter transformation enables achieving low breakdown voltage (5V or less) while maintaining low leakage current, as the graded profile reduces electron tunneling compared to heavily doped abrupt junctions.
2Strength
If a p-n junction Zener diode with heavily doped regions is used to achieve low breakdown voltage, then the reverse breakdown voltage is reduced, but the junction capacitance increases
Solution Approach 1:
The patent uses parameter changes by implementing a linearly graded P-region doping profile instead of a uniform heavy doping profile. This graded structure achieves the desired low breakdown voltage while reducing the junction capacitance compared to conventional heavily doped Zener diodes, as the gradual doping transition reduces the depletion region discontinuity and associated capacitance.
3Reliability
If a vertical N+/P/N+ punch-thru device structure is used, then the ESD protection is provided, but tight control of the P region widths is required to maintain low punch-thru voltage and clamp voltage
Solution Approach 1:
The patent transforms the uniform P-region doping parameter into a linearly graded doping profile, which changes how the punch-thru voltage responds to dimensional variations. The graded profile provides a more gradual electric field distribution that reduces sensitivity to P-region width variations, thereby relaxing manufacturing precision requirements while maintaining reliable ESD protection and predictable voltage characteristics.
4Ease of manufacture
If a vertical N+/P+/P−/N+ structure with lightly doped P− region is used, then the structure is formed, but the reverse breakdown voltage becomes high
Solution Approach 1:
The patent applies parameter changes by replacing the lightly doped P− region with a linearly graded P-region that transitions from lower doping near the P+ region to higher doping toward the N+ region. This parameter transformation maintains the structural simplicity and ease of manufacture while achieving low reverse breakdown voltage (5V or less), as the graded profile creates appropriate electric field distribution for low-voltage breakdown without requiring additional lightly doped regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively protects integrated circuits from ESD events with low leakage, low capacitance, and controlled reverse breakdown voltage, ensuring rapid activation and efficient current dissipation for both positive and negative discharges at low voltages.
Implementation Method 1
The linearly graded P-region, which has a doping profile that varies linearly from the P+ sidewall or field implant to the other junction, provides an avalanche injection path that quickly turns on the transistor
Implementation Method 2
This p-n Zener diode, shown in FIG. 1(a)2 by implanting an N-doped area 112 into a P+ doped substrate 114. This zener diode 100 when reverse biased operates in the avalanche breakdown regime and conducts current.
Data Source
AI summary
The present invention describes ESD apparatus, methods of forming the same, and methods of providing ESD protection. In certain aspects, the invention achieves the desired turn-on voltage and maintains low leakage in the ESD apparatus, and the methods of providing ESD protection. In one aspect, a zener diode that has a positive trigger voltage is used to quickly turn-on a transistor. In another aspect, different zener diodes that have positive and negative trigger voltages, respectively, are used to quickly turn on a transistor. In still another aspect, a linearly graded P-region is used to implement the ESD device of the present invention.