Graded Phosphorus Doping in NFET Source-Drain Regions

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Solution Overview

Problem

The abrupt phosphorous (P) dopant concentration transition from the channel to the extension region in n-type field-effect transistors (NFETs) leads to low breakdown voltage (BV) and high substrate current (Isub), which are not adequately addressed by traditional implant condition tuning methods.

Innovation Solution

The formation of multiple-step epi-SiP or epi-SiC/epi-SiP source/drain (S/D) structures with consecutive epi-Si layers doped at increasing dosages of P, achieving a graded P dopant concentration distribution from the channel to the extension region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If a single epi-SiP layer with high P concentration is used to boost DC performance, then DC performance is improved, but breakdown voltage decreases and substrate current increases

Engineering Contradiction:
ImproveDC performanceVSAvoidbreakdown voltage
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The single epi-SiP layer is segmented into multiple epi-Si layers with progressively increasing P concentrations. This segmentation allows the device to achieve both high DC performance (through overall high doping) and high breakdown voltage (through gradual concentration transition) by dividing the doping function across multiple layers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the S/D structure are assigned different P concentrations locally. The lower epi-Si layers have lower P concentrations to ensure high breakdown voltage and low substrate current, while the upper epi-Si layers have higher P concentrations to provide strong DC performance. This local quality differentiation resolves the contradiction between DC performance and reliability.

Inventive Principle:
Principle #3Local quality

2Reliability

If implant conditions are tuned to reduce doping profile steepness, then breakdown voltage improves, but DC performance degrades

Engineering Contradiction:
Improvebreakdown voltageVSAvoidDC performance
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

Instead of uniformly reducing doping steepness through implant condition tuning, the patent changes the parameter of doping concentration distribution by using multiple epi layers with progressively increasing P concentrations. This allows the doping profile to be gradual (improving breakdown voltage) while still achieving high overall doping (maintaining DC performance).

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The S/D structure uses a composite of multiple epi-Si layers doped at different P concentrations rather than a single uniform material. This composite structure enables simultaneous optimization of both breakdown voltage (through the gradual transition from lower to upper layers) and DC performance (through the cumulative high doping effect).

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances breakdown voltage and reduces substrate current, improving the overall performance of NFET devices by creating a more gradual dopant transition.

Implementation Method 1

performing in-situ doping of P for each epi-Si layer, wherein consecutive epi-Si layers are doped at increasing dosages of P

Methodology Applied
Scientific EffectIn-situ doping:

Data Source

PatentUS9966433B2Multiple-step epitaxial growth S/D regions for NMOS FinFET
Publication Date: 2018.05.08 GLOBALFOUNDRIES US INC
  • US9966433B2 patent drawing
  • US9966433B2 patent drawing
  • US9966433B2 patent drawing

AI summary

A method of forming NFET S/D structures with multiple layers, with consecutive epi-SiP layers being doped at increasing dosages of P and the resulting device are provided. Embodiments include forming multiple epi-Si layers in each S/D cavity of a NFET; and performing in-situ doping of P for each epi-Si layer, wherein consecutive epi-Si layers are doped at increasing dosages of P.