Graded Semiconductor Stressor for Mobility Enhancement
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Solution Overview
Problem
Current semiconductor processing methods face challenges in achieving selective epitaxial deposition of strained semiconductor layers, particularly in recessed source and drain regions, due to non-substitutional doping and dislocation issues, which affect the strain-induced mobility enhancements in NMOS and PMOS devices.
Innovation Solution
A method involving graded semiconductor stressors with varying impurity concentrations is used, where the upper portion of the stressor in recessed regions has a higher strain than the lower portion, extending to the sidewalls, achieved through cyclical blanket deposition and selective etching, allowing for targeted strain induction in heteroepitaxial layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If substitutional doping is used to introduce strain into silicon-containing materials, then electron and hole mobility are enhanced, but dislocation defects and non-substitutional doping issues occur
Solution Approach 1:
The patent applies local quality by creating a graded stressor where the impurity concentration varies spatially - higher at the upper portion near the channel and lower at the lower portion. This localized variation in composition allows strain to be concentrated where it is most needed for mobility enhancement while reducing overall impurity content and minimizing dislocation defects throughout the structure.
Solution Approach 2:
The patent utilizes parameter changes by gradually varying the impurity concentration within the stressor material from the lower portion to the upper portion. This graded composition profile transitions the lattice constant gradually, enabling strain induction while avoiding abrupt interfaces that would generate dislocations, thus maintaining doping precision.
2Reliability
If heteroepitaxial deposition is used to form strained layers, then strain-induced mobility enhancement is achieved, but selective deposition and etching complexity increases
Solution Approach 1:
The patent employs periodic action through cyclical sequences of deposition and selective etching steps. Multiple deposition cycles build up the graded stressor layer with varying impurity concentrations, followed by selective etching cycles that remove material from specific regions. This periodic process enables precise control over the stressor profile while managing the complexity of selective deposition.
Solution Approach 2:
The patent applies segmentation by dividing the stressor formation into discrete deposition and etching cycles, each creating or refining a specific portion of the graded structure. The process segments the complex task of forming a graded stressor with precise impurity distribution into manageable sequential steps, reducing overall process complexity.
3Manufacturing precision
If graded stressors with varying impurity concentrations are used, then dislocation defects are reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent utilizes parameter changes by implementing a graded impurity concentration profile within the stressor material. The impurity concentration varies continuously or in steps from the lower portion to the upper portion, creating a gradual transition in lattice constant that reduces dislocation defects. This parameter variation is achieved through controlled deposition processes.
Solution Approach 2:
The patent employs periodic deposition and etching cycles to build the graded stressor structure. Each cycle deposits a layer with a specific impurity concentration, and subsequent selective etching refines the profile. This periodic process enables precise control over the graded structure, reducing defects while managing manufacturing complexity through systematic repetition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables enhanced electron and hole mobility by localized strain distribution, reducing dislocation defects and improving the performance of semiconductor devices without excessive impurity content, thus optimizing the strain-induced effects in NMOS and PMOS devices.
Implementation Method 1
Heteroepitaxy involves depositing thin layers of a particular crystalline material onto a different crystalline material in such a way that the deposited layer adopts the lattice constant of the underlying crystal material.
Implementation Method 2
Portions of the semiconductor material are selectively removed from the sidewall surfaces of the recessed region while leaving a heteroepitaxial layer of the semiconductor material over the bottom surfaces
Implementation Method 3
Because the germanium atoms are slightly larger than the silicon atoms and the deposited heteroepitaxial silicon germanium is constrained to the smaller lattice constant of the silicon beneath it, the silicon germanium is compressively strained
Data Source
AI summary
A semiconductor substrate having recesses filled with heteroepitaxial silicon-containing material with different portions having different impurity concentrations. Strained layers can fill recessed source/drain regions in a graded, bottom-up fashion. Layers can also line recess sidewalls with one concentration of strain-inducing impurity and fill the remainder to the recess with a lower concentration of the impurity. In the latter case, the sidewall liner can be tapered.