Graded SiGe Buffer Layer for High-Mobility Transistors
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Solution Overview
Problem
As feature sizes of MOS transistors decrease, the channel length reduces, leading to increased electric charge scattering and decreased mobility, which hampers the improvement of transistor saturation current.
Innovation Solution
A semiconductor device with a substrate and a strain released layer having a larger lattice constant than the underlying layer, combined with a strain relaxed buffer layer, where the lattice constant decreases from the interface with the underlying layer to the strain relaxed buffer layer, promoting improved charge mobility by reducing dislocation density and strain release.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length of the transistor is reduced to improve integration density, then the feature size decreases and more devices can be packed, but electric charge scattering increases and mobility decreases
Solution Approach 1:
The patent applies local quality by creating a graded buffer layer where the lattice constant varies locally from the substrate interface to the surface. This gradient structure provides different lattice matching conditions at different depths, allowing the channel region to have optimized lattice properties for high mobility while maintaining overall device integration density.
Solution Approach 2:
The patent changes the lattice constant parameter continuously or stepwise through the buffer layer thickness. By controlling the composition gradient (e.g., SiGe to Si transition), the lattice constant is adjusted to reduce dislocation density and improve charge mobility in the channel region, thereby resolving the contradiction between integration density and charge mobility.
2Reliability
If a graded buffer layer with varying lattice constant is introduced to improve charge mobility, then dislocation density is reduced and mobility increases, but the device structure becomes more complex
Solution Approach 1:
The patent segments the buffer layer into multiple sub-layers with different lattice constants (e.g., first graded buffer layer and second graded buffer layer). This segmentation allows progressive lattice matching improvement while managing the complexity through modular layering, where each segment contributes to reducing dislocation density in a controlled manner.
Solution Approach 2:
The patent addresses the complexity issue by extending the solution into the vertical dimension with a graded buffer layer structure. Instead of complicating the planar device layout, the lattice constant gradient is applied in the thickness direction, thereby improving charge mobility without significantly increasing in-plane device complexity.
3Reliability
If multiple graded buffer layers are stacked to further reduce dislocation density, then charge mobility improves, but the manufacturing process becomes more difficult
Solution Approach 1:
The patent applies preliminary action by pre-designing the graded buffer layer structure with controlled composition gradients before channel formation. The lattice constant is gradually adjusted in advance through the buffer layers, preventing dislocation propagation to the channel region. This preliminary lattice optimization simplifies subsequent manufacturing steps by ensuring a high-quality substrate for channel deposition.
Solution Approach 2:
The graded buffer layers act as intermediary structures between the substrate and the channel region. These intermediate layers with varying lattice constants mediate the transition, reducing the abrupt lattice mismatch that would otherwise cause high dislocation density. This intermediary approach simplifies manufacturing by providing a gradual transition zone that is easier to grow epitaxially than direct abrupt interfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances charge mobility and reduces dislocation density, thereby improving the performance and efficiency of semiconductor devices by optimizing the lattice structure and strain release in the semiconductor substrate.
Implementation Method 1
The strain released layer has a lattice constant that is larger than a lattice constant of a directly underlying layer at an interface therewith
Implementation Method 2
The lattice constant of the strain released layer decreases from the interface with the underlying layer to an interface with the strain relaxed buffer layer directly thereon
Data Source
AI summary
A semiconductor substrate and a semiconductor device are provided. The semiconductor substrate includes a base substrate, a first silicon germanium layer on the base substrate and a second silicon germanium layer on the first silicon germanium layer. A germanium fraction of the second silicon germanium layer decreases in the direction away from the base substrate, and a germanium fraction of a lowermost part of the second silicon germanium layer is greater than a germanium fraction of an uppermost part of the first silicon germanium layer.