Stress-Enhanced MOS Transistor via Graded SiGe Trench Fill

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Solution Overview

Problem

As integrated circuits shrink to smaller sizes, the performance of MOS transistors degrades due to scaling, and conventional methods for enhancing stress in transistors, such as increasing germanium content in SiGe, lead to surface loss and stress relaxation, failing to achieve sufficient mobility gains.

Innovation Solution

A stress-enhanced MOS transistor is fabricated by embedding SiGe with a high germanium concentration in the trench sidewalls adjacent to the channel and a low germanium concentration on the surface, using selective epitaxial growth to achieve a thicker high germanium concentration SiGe layer on the sidewalls, which exerts greater stress on the channel than a uniformly low germanium concentration fill would.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If germanium content in SiGe is increased to enhance stress and mobility, then channel stress and carrier mobility are improved, but surface germanium loss, agglomeration, and stress relaxation occur

Engineering Contradiction:
Improvecarrier mobilityVSAvoidsurface germanium loss
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The patent applies local quality by creating a non-uniform germanium concentration distribution within the SiGe embedded layer. The germanium concentration is highest at the interface with the silicon substrate and decreases toward the surface, forming a gradient structure. This localized variation in composition optimizes stress application to the channel while preventing surface germanium loss and agglomeration, as the lower surface concentration reduces surface energy and instability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the germanium concentration parameter across the thickness of the SiGe layer. Instead of using a uniform composition, the germanium content varies from approximately 20-50% at the substrate interface to lower values at the surface. This parameter gradient allows the embedded layer to exert sufficient stress on the channel for enhanced mobility while avoiding the harmful effects of high surface germanium concentration.

Inventive Principle:
Principle #35Parameter changes

2Stress or pressure

If germanium content in SiGe is increased to enhance stress, then longitudinal stress on channel is increased, but stress relaxation occurs during fabrication

Engineering Contradiction:
Improvelongitudinal stress on channelVSAvoidstress relaxation
Core Design Contradiction:
Stress or pressureVSStability of the object's composition

Solution Approach 1:

The patent implements local quality through a graded germanium concentration profile where the highest germanium content (and thus highest stress generation) is located at the substrate interface rather than uniformly distributed. This localized stress generation at the critical channel interface maximizes the stress effect on carriers while the lower surface concentration provides compositional stability during subsequent fabrication processing, preventing stress relaxation.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent creates a composite structure within the SiGe embedded layer by combining regions of different germanium concentrations. The lower germanium concentration region near the surface provides structural stability and resistance to stress relaxation during fabrication, while the higher germanium concentration region at the substrate interface provides the necessary longitudinal stress to the channel for enhanced carrier mobility.

Inventive Principle:
Principle #40Composite materials

3Ease of manufacture

If trench is refilled with uniform SiGe to simplify fabrication, then manufacturing is easier, but insufficient stress is exerted on channel

Engineering Contradiction:
Improvefabrication simplicityVSAvoidstress on channel
Core Design Contradiction:
Ease of manufactureVSStress or pressure

Solution Approach 1:

The patent applies parameter changes by varying the germanium concentration during the epitaxial growth process. The germanium content is gradually reduced from the substrate interface toward the surface, creating a compositional gradient. This parameter variation can be implemented through controlled changes in gas flow rates or precursor ratios during selective epitaxial growth, achieving the desired stress profile with modified but still practical fabrication processes.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses local quality by creating a SiGe embedded layer with spatially varying germanium concentration. The region adjacent to the channel interface has higher germanium content to maximize stress, while the surface region has lower germanium content. This local differentiation of composition optimizes stress application without requiring complete process redesign, as it can be achieved through standard epitaxial growth parameter modulation.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach optimizes channel stress and mobility gain, avoiding the issues of surface germanium concentration problems and achieving enhanced majority carrier mobility without the limitations of conventional methods.

Implementation Method 1

applying a longitudinal stress to the channel of an MOS transistor can increase the mobility; a compressive longitudinal stress enhances the mobility of majority carrier holes

Methodology Applied
Scientific EffectStress:

Implementation Method 2

the trench is refilled by using selective epitaxial growth of the SiGe

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS7534689B2Stress enhanced MOS transistor and methods for its fabrication
Publication Date: 2009.05.19 SEMIFAB IP INNOVATIONS LLC
  • US7534689B2 patent drawing
  • US7534689B2 patent drawing
  • US7534689B2 patent drawing

AI summary

A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.