Graded SiGe Embedded Process for PMOS Dislocation Control

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Solution Overview

Problem

In semiconductor manufacturing, the high Ge content in SiGe layers can lead to lattice mismatch and dislocation at the interface with the substrate, degrading PMOS device performance, and also affects the growth and reactivity of the cap layer, resulting in poor contact and increased resistance.

Innovation Solution

The embedded SiGe process involves growing multiple layers with varying Ge content, starting with a seed layer, followed by increasing Ge content in the first transition layer, maintaining high Ge in the middle layer, and then decreasing Ge in the second transition layer, culminating in a cap layer, to reduce dislocation and enhance cap layer growth and reactivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high Ge content is used in SiGe layers to improve PMOS device performance, then device performance is improved, but lattice mismatch and dislocation occur at the interface with the substrate

Engineering Contradiction:

ImprovePMOS device performanceVSAvoidinterface quality

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The SiGe layer is segmented into multiple layers with progressively increasing Ge content (first SiGe layer with 1-10% Ge, second SiGe layer with 10-30% Ge, third SiGe layer with 30-50% Ge). This gradual segmentation reduces lattice mismatch at each interface compared to a single high-Ge layer, preventing dislocation while achieving the desired compressive stress for PMOS performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the SiGe structure have different Ge content tailored to local requirements: lower Ge content near the substrate interface to minimize mismatch, and higher Ge content in upper layers to provide compressive stress. This local quality variation optimizes both interface quality and device performance simultaneously.

Inventive Principle:

Principle #3Local quality

2Reliability

If high Ge content in SiGe layers is used to improve device performance, then compressive stress is maintained, but cap layer growth and reactivity are affected, resulting in poor contact and increased resistance

Engineering Contradiction:

Improvedevice performanceVSAvoidcap layer contact quality

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

Instead of placing the highest Ge content layer directly adjacent to the cap layer (which would harm cap layer growth), the structure inverts the Ge content gradient: highest Ge content (30-50%) is in the third SiGe layer away from the cap interface, while the cap layer is deposited on a lower Ge content surface. This inversion protects cap layer quality while maintaining overall compressive stress for device performance.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The structure uses a composite of multiple SiGe layers with different Ge content, combined with a cap layer, to achieve both compressive stress (from high-Ge layers) and good cap layer contact (from lower-Ge interface). This composite structure resolves the conflict between stress requirements and contact quality.

Inventive Principle:

Principle #40Composite materials

3Manufacturing precision

If multiple layers with varying Ge content are grown to reduce dislocation, then interface quality is improved, but process complexity increases

Engineering Contradiction:

Improveinterface qualityVSAvoidprocess complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent systematically changes the Ge content parameter across three distinct layers (1-10%, 10-30%, 30-50%), creating a controlled gradient that reduces dislocation. While this adds layers, each layer follows the same deposition process, so the complexity increase is manageable and justified by the significant improvement in interface quality and device performance.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces dislocation between the substrate and SiGe layers, improves cap layer growth, and enhances device performance by maintaining compressive stress and reducing parasitic resistance, while being compatible with existing CMOS processing.

Implementation Method 1

growing multiple layers with varying Ge content, starting with a seed layer, followed by increasing Ge content in the first transition layer

Methodology Applied

Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 2

HIGH PRESSURE LOW THERMAL BUDGE HIGH-K POST ANNEALING PROCESS

Methodology Applied

Scientific EffectAnnealing: Annealing

Data Source

PatentUS10727341B2High pressure low thermal budge high-k post annealing process

Publication Date: 2020.07.28 SHANGHAI HUALI MICROELECTRONICS CORP

AI summary

A method of embedding SiGe when fabricating a PMOS device is provided. Multiple layers of SiGe layers with different Ge contents may be formed such that the Ge content increases to from bottom layer(s) to middle layer(s), and decreases from the middle layer(s) to top layer(s). In some embodiments, the embedded SiGe can have a SiGe seed layer over a substrate, a first SiGe transition layer over the SiGe seed layer, a SiGe milled layer over the first SiGe transition layer, and a second SiGe transition layer over the SiGe middle layer. The first SiGe transition layer can have a Ge content increasing from a bottom of the first SiGe transition layer to a top of the first SiGe transition layer. The second SiGe transition layer can have a Ge content decreasing from a bottom of the second SiGe transition layer to a top of the second SiGe transition layer.