Graded SiGe Layer Reduces Stacking Faults in PMOS
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Solution Overview
Problem
High Ge content in embedded SiGe source/drain regions leads to substantial stacking faults in semiconductor devices, deteriorating PMOS performance.
Innovation Solution
A method involving the formation of a recess in a Si substrate with a first SiGe layer having a gradually increasing Ge content from bottom to top, a SiGe seed layer on sidewalls, and a second SiGe layer with uniform Ge content, where the Ge content in the seed layer is less than in the second SiGe layer, to reduce or eliminate stacking faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the content of Ge in the embedded SiGe material is increased to apply higher compressive stress to the channel region, then PMOS device performance is improved, but substantial stacking faults occur on the interface between Si and SiGe, deteriorating device performance
Solution Approach 1:
The patent applies different Ge content distributions to different regions: the first SiGe layer has Ge content that gradually increases from bottom to top, while the second SiGe layer has uniform high Ge content. This local quality variation allows the interface region to have gradual composition changes (reducing stacking faults) while the upper region maintains high Ge content (providing necessary compressive stress for PMOS performance).
Solution Approach 2:
The patent changes the Ge content parameter through the thickness of the first SiGe layer, transitioning from low Ge content at the bottom to high Ge content at the top. This parameter gradient reduces the abruptness of composition changes at the Si-SiGe interface, thereby reducing stacking faults while still achieving high Ge content in the embedded SiGe source/drain regions for effective stress application.
2Reliability
If high content of Ge is used in embedded SiGe source/drain regions to enhance carrier mobility, then driving current increases, but stacking faults occur at the Si-SiGe interface
Solution Approach 1:
The patent implements local quality by creating a Ge content gradient in the first SiGe layer that is in contact with the Si substrate, while maintaining high uniform Ge content in the second SiGe layer. This allows the interface region to have favorable composition characteristics for reducing stacking faults, while the bulk SiGe material maintains high Ge content for enhancing carrier mobility in the source/drain regions.
Solution Approach 2:
The embedded SiGe structure is segmented into two distinct layers: the first SiGe layer with gradual Ge content increase and the second SiGe layer with uniform high Ge content. This segmentation allows each layer to fulfill different functions - the first layer minimizes interface defects while the second layer provides the necessary Ge content for carrier mobility enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces or eliminates stacking faults while maintaining high Ge content in SiGe source/drain regions, thereby enhancing PMOS device performance.
Implementation Method 1
One effective mechanism for improving carrier mobility is to produce stress in a channel region. By embedding SiGe material in PMOS source and drain regions, embedded SiGe techniques may apply compressive stress to the channel region, causing significant PMOS performance improvement.
Implementation Method 2
forming a first SiGe layer on the bottom of the recess, wherein the content of Ge in the first SiGe layer is gradually increased from bottom to top of the first SiGe layer
Data Source
AI summary
This invention relates to a semiconductor device and a manufacturing method thereof for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom, a SiGe seed layer is formed on sidewalls of the recess and a second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer.