Graded Silicon Nitride SONOS Structure for Fast Erasing

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Solution Overview

Problem

Conventional SONOS structures face challenges in achieving high erasing speed, charge retention, and endurance under a lower electric field due to the limitations of the tunneling oxide layer, which leads to electron injection from the substrate under high erasing voltage, affecting the erasing efficiency.

Innovation Solution

A SONOS structure with a thin graded silicon nitride layer having a graded Si/N content and a tapered bandgap structure is introduced, replacing the conventional blocking oxide layer, to reduce the erasing voltage and enhance the erasing speed by using a stacked OTNO layer comprising a second silicon oxide layer, a thin graded silicon nitride layer, and a third silicon oxide layer, which offsets the bandgap and suppresses electron injection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a thinner tunneling oxide layer is used to enhance program and erasing speed, then the erasing speed is improved, but the charge retention ability and program/erase endurance deteriorate

Engineering Contradiction:

Improveerasing speedVSAvoidcharge retention ability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The blocking oxide layer is segmented into a stacked structure comprising a first silicon oxide layer, a charge trapping silicon nitride layer, and a second silicon oxide layer. This segmentation allows the first silicon oxide layer to enable fast erasing while the charge trapping silicon nitride layer and second silicon oxide layer work together to improve charge retention and endurance, thus resolving the contradiction between speed and reliability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The blocking oxide layer is replaced with a composite stacked structure of silicon oxide and silicon nitride layers. The silicon nitride layer provides charge trapping capability that enhances reliability, while the silicon oxide layers maintain the blocking function, achieving both fast erasing speed and good charge retention through material composition

Inventive Principle:

Principle #40Composite materials

2Reliability

If a thicker tunneling oxide layer is used to improve charge retention, then the charge retention ability is improved, but the erasing speed deteriorates due to larger electric field requirements

Engineering Contradiction:

Improvecharge retention abilityVSAvoiderasing speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The blocking oxide layer is divided into multiple functional layers: the first silicon oxide layer provides efficient hole tunneling path for fast erasing, while the charge trapping silicon nitride layer and second silicon oxide layer provide charge retention. This segmentation allows each layer to optimize for its specific function, achieving both fast erasing and good charge retention simultaneously

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the blocking oxide structure are assigned different materials with optimized properties: the first silicon oxide layer is optimized for hole tunneling (fast erasing), while the charge trapping silicon nitride layer is optimized for charge storage (retention). This local quality differentiation resolves the speed-retention contradiction

Inventive Principle:

Principle #3Local quality

3Speed

If a higher electric field is applied to achieve faster erasing, then the erasing speed is improved, but electron injection from the substrate increases causing erase saturation

Engineering Contradiction:

Improveerasing speedVSAvoidelectron injection from substrate

Core Design Contradiction:

SpeedVSObject-generated harmful factors

Solution Approach 1:

The charge trapping silicon nitride layer acts as an intermediary between the first silicon oxide layer and the substrate. It provides a preferential trapping path for holes during erasing, mediating the charge transport process to prevent electrons from being injected into the charge storage layer, thus enabling fast erasing without erase saturation

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The bandgap structure is modified by introducing the charge trapping silicon nitride layer, which changes the energy band alignment. This parameter change creates a more favorable condition for hole tunneling while raising the barrier for electron injection, allowing fast erasing speed without the harmful electron injection effect

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The tapered bandgap structure reduces the required erasing voltage, enhances erasing speed, and improves charge retention by minimizing electron injection from the substrate, thereby improving the overall performance of the SONOS device.

Implementation Method 1

A recently developed SONOS structure utilizes a charge trapping silicon nitride layer instead of the conventional polysilicon floating gate to store the charges. Since the silicon nitride layer utilizes trapping levels to store charges, the charges stored in the silicon nitride layer will distribute discretely.

Methodology Applied

Scientific EffectCharge trapping:

Implementation Method 2

The SONOS structure uses electron tunneling for data programming and hole injection for data erasing.

Methodology Applied

Scientific EffectElectron tunneling:

Implementation Method 3

Methodology Applied

Scientific EffectBandgap offset:

Data Source

PatentUS8659071B2Method and structure to improve the erasing speed operation of SONOS memory device having a graded silicon nitride layer

Publication Date: 2014.02.25 SHANGHAI HUALI MICROELECTRONICS CORP

AI summary

The invention provides a SONOS structure, a manufacturing method thereof and a semiconductor device with the SONOS structure. The SONOS structure comprises: a first tunneling oxide layer formed on a substrate, a charge storage silicon nitride layer, a second silicon oxide layer, a thin graded silicon nitride layer having graded Si/N content formed on the second silicon oxide layer, a third silicon oxide layer formed on the thin graded silicon nitride layer, and a polysilicon control gate. The Si/N content ratio of the silicon nitride of the thin graded silicon nitride layer increases gradually, wherein the silicon nitride of the graded silicon nitride layer closer to the second silicon oxide layer contains higher nitride content, and the silicon nitride of the graded silicon nitride layer closer to the third silicon oxide layer contains higher silicon content.