Graded Source/Drain Structure for Low-Resistance Ge N-Channel Contacts
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Solution Overview
Problem
The challenge in developing integrated circuit structures with germanium N-channels is the high contact resistance due to lattice mismatch between silicon and germanium, leading to increased defect concentrations and reduced dopant concentration, which limits the performance of n-type Ge channel devices.
Innovation Solution
The implementation of compositionally graded source/drain regions with a transition from a phosphorous-doped Ge-rich SiGe interface layer to a P-doped Si layer, minimizing defect formation and smoothing out k-space mismatch, thereby reducing contact resistance and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon and germanium are directly interfaced to form source/drain structures, then device fabrication is simplified, but contact resistance increases due to lattice mismatch
Solution Approach 1:
A compositionally graded SiGe intermediate layer is introduced between the silicon substrate and germanium source/drain regions. This intermediate layer acts as a mediator that gradually transitions the lattice constant from silicon to germanium, reducing lattice mismatch and minimizing defect formation at the interfaces, thereby lowering contact resistance while maintaining fabrication feasibility.
Solution Approach 2:
The lattice constant is gradually changed through a compositionally graded SiGe layer where the germanium concentration varies continuously from 0% at the silicon interface to 100% at the germanium source/drain interface. This parameter change approach smooths out the abrupt lattice mismatch, reducing scattering events and contact resistance.
2Reliability
If high dopant concentration is used in source/drain regions, then contact resistance decreases, but defect concentration increases due to lattice mismatch
Solution Approach 1:
The compositionally graded SiGe intermediate layer serves as an intermediary that allows high dopant concentration to be introduced gradually. By transitioning the composition from silicon to germanium, the layer accommodates dopant atoms more effectively, reducing defect formation while maintaining high dopant concentration necessary for low contact resistance.
Solution Approach 2:
The germanium concentration parameter is varied continuously in the graded layer, which changes the lattice constant and dopant solubility gradually. This allows high dopant concentration to be achieved with reduced defect concentration compared to abrupt interfaces, as the gradual parameter change reduces lattice strain and dislocation formation.
3Productivity
If conventional fabrication processes are extended to 10nm node, then manufacturing continuity is maintained, but variability increases limiting further scaling
Solution Approach 1:
A composite structure comprising silicon substrate, compositionally graded SiGe intermediate layer, and germanium source/drain regions is implemented. This composite material approach combines the advantages of silicon (mature fabrication processes) with germanium (high carrier mobility), enabling continued manufacturing at 10nm node while reducing process variability through the graded transition layer that minimizes interface defects.
Data Source
AI summary
Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.