Graded Strain-Inducing Semiconductor Region for Transistor Performance
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Solution Overview
Problem
The reduction of channel length in transistors to enhance operating speed is hindered by increased leakage currents and inferior controllability due to the use of high-k dielectric materials, which also degrade charge carrier mobility, and the incorporation of strain-inducing silicon/germanium materials can lead to lattice defects and process non-uniformities.
Innovation Solution
A graded strain-inducing semiconductor material with varying germanium concentration is embedded in transistors, where a highly strained material is formed along the sidewalls of cavities with a smooth transition to the channel region, reducing lattice defects and enhancing strain transfer, while a lower germanium concentration is used at the surface to minimize defects and processing complexities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high-k dielectric materials are used in gate electrode structures, then capacitive coupling is enhanced, but charge carrier mobility is degraded and leakage currents increase
Solution Approach 1:
The patent applies local quality by creating a graded strain-inducing semiconductor material with varying germanium concentration throughout the cavity depth. The material has high germanium concentration (high strain) at the bottom near the channel region and low germanium concentration (low strain) at the top near the surface. This spatial variation in material properties enables simultaneous achievement of high capacitive coupling from high-k dielectric and maintained charge carrier mobility through localized strain at the critical interface region.
2Speed
If channel length is reduced to increase operating speed, then operating speed is improved, but controllability and leakage current performance deteriorate
Solution Approach 1:
The patent applies parameter changes by modifying the strain-inducing material parameters (germanium concentration) as a function of position within the cavity. By changing the material composition parameter from uniform to graded (varying with depth), the patent achieves enhanced strain transfer to the channel region in short-channel transistors, maintaining charge carrier mobility and controllability even when channel length is reduced for higher operating speed.
3Reliability
If strain-inducing silicon/germanium materials are incorporated to enhance charge carrier mobility, then charge carrier mobility is improved, but lattice defects and process non-uniformities increase
Solution Approach 1:
The patent applies local quality by concentrating the strain-inducing material with high germanium concentration at the bottom portion of the cavity where it can most effectively strain the channel region, while using low germanium concentration material at the top portion. This localized approach provides high strain where needed (improving charge carrier mobility) while minimizing the overall amount of lattice-mismatched material (reducing lattice defects and process non-uniformities).
Solution Approach 2:
The patent applies parameter changes by varying the germanium concentration parameter continuously or in steps from the bottom to the top of the cavity. This graded parameter change enables smooth transition between high-strain and low-strain regions, reducing abrupt interfaces that could generate dislocations and lattice defects, while maintaining effective strain transfer to enhance charge carrier mobility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves transistor performance by increasing charge carrier mobility and reducing lattice defects, achieving superior strain conditions and performance gains in transistors with gate lengths of 40 nm and less, even with high-k dielectric materials, by optimizing the strain-inducing mechanism through selective epitaxial growth techniques.
Implementation Method 1
a first strain-inducing semiconductor material having a first lattice mismatch with respect to the semiconductor base material
Implementation Method 2
selective epitaxial growth techniques
Implementation Method 3
a lateral growth rate varying from bottom to top of sidewalls of the cavity so as to be lowest at the top of the cavity
Data Source
AI summary
In sophisticated semiconductor devices, transistors may be formed on the basis of an efficient strain-inducing mechanism by using an embedded strain-inducing semiconductor alloy. The strain-inducing semiconductor material may be provided as a graded material with a smooth strain transfer into the neighboring channel region in order to reduce the number of lattice defects and provide enhanced strain conditions, which in turn directly translate into superior transistor performance. The superior architecture of the graded strain-inducing semiconductor material may be accomplished by selecting appropriate process parameters during the selective epitaxial growth process without contributing to additional process complexity.