Graded TFT Gate Dielectric for Leakage and Charge Trap Control
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Solution Overview
Problem
As integrated circuits scale downward in size, process variations lead to inconsistent transistor performance and low yield due to variations in interconnect structures such as gate structures, drain regions, and source regions, affecting the formation of backend structures.
Innovation Solution
The use of multilayer and concentration gradient gate dielectrics in thin film transistor structures to tune performance and reliability by reducing source/drain current leakage and minimizing charge traps, achieved through the formation of multiple compositionally different dielectric layers and material gradients within the gate dielectric.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If process variations are reduced through conventional single-layer gate dielectric, then manufacturing precision improves, but device performance and reliability deteriorate due to insufficient control of charge traps and current leakage
Solution Approach 1:
The gate dielectric is divided into multiple layers with different materials and compositions. Each layer serves specific functions: the first layer (higher dielectric constant) provides strong electric field control, while the second layer (lower dielectric constant) reduces charge traps and improves interface quality. This segmentation allows independent optimization of each layer's properties to address both manufacturing precision and device reliability.
Solution Approach 2:
Different regions of the gate dielectric structure are assigned different material compositions tailored to local requirements. The first gate dielectric layer uses materials with higher dielectric constants (e.g., HfO2, ZrO2) for superior gate control, while the second layer uses materials with lower dielectric constants (e.g., SiO2, SiN) for improved interface quality and reduced charge trapping. This local quality differentiation simultaneously improves manufacturing precision and device reliability.
2Reliability
If multilayer gate dielectric is implemented to improve device performance, then reliability improves, but device complexity increases
Solution Approach 1:
The complex requirements for gate dielectric performance are extracted and distributed across two separate layers. Instead of attempting to satisfy all requirements in a single layer, the invention separates the functions: charge control is extracted to the first layer while interface quality and charge trap reduction are extracted to the second layer. This extraction approach manages complexity by dividing functionality while improving reliability.
Solution Approach 2:
The gate dielectric employs a composite structure combining two different dielectric materials with complementary properties. The first layer uses high-k materials for superior gate control, while the second layer uses low-k or nitride materials for interface passivation and charge trap reduction. This composite material approach achieves enhanced reliability through synergistic material properties while managing structural complexity through systematic layer integration.
3Reliability
If gate dielectric layers are optimized for minimal charge traps, then device reliability improves, but manufacturing precision deteriorates due to increased process complexity
Solution Approach 1:
The gate dielectric structure is designed with preliminary optimization for charge trap reduction. The second layer is specifically engineered with materials and thicknesses that proactively address charge trap formation at the gate dielectric-semiconductor interface. By incorporating this preliminary action into the structure design, the system achieves improved reliability while managing manufacturing precision through predetermined material selections and deposition parameters.
Data Source
AI summary
Techniques are provided herein for forming thin film transistor structures having a multilayer and/or concentration gradient gate dielectric. Such a gate dielectric can be used, to tune the performance and/or reliability of the transistor. According to some such embodiments, memory structures having thin film transistor (TFT) structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include a multilayer and/or graded gate dielectric that includes at least two or more different dielectric layers and/or a material concentration gradient through a thickness of the gate dielectric.