Gradient-Doped Barrier Layer for Compact Latch-Up Isolation

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Solution Overview

Problem

High-voltage devices are susceptible to interference due to unwanted cross talk between adjacent power devices, leading to parasitic effects like latch-up, which can cause product failure, and reducing the distance between regions to mitigate this issue undesirably enlarges chip size.

Innovation Solution

A semiconductor structure with a modified substrate that includes a barrier layer with a gradient doping profile and an epitaxial layer, along with isolation structures, to suppress electron carrier injection and reduce lateral parasitic current, thereby minimizing latch-up without increasing chip size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the distance between adjacent power devices is reduced to mitigate cross talk interference, then latch-up effects are suppressed, but chip size undesirably enlarges

Engineering Contradiction:
Improvelatch-up suppressionVSAvoidchip size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

An intrinsic semiconductor layer is introduced as an intermediary between the first and second power devices. This layer acts as a mediator that blocks parasitic current paths and suppresses latch-up effects without requiring increased spacing between devices, thereby maintaining compact chip size while improving reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The solution transitions from addressing interference in the horizontal plane (by increasing device spacing) to addressing it in the vertical dimension (by introducing an intrinsic layer between substrate and devices). This dimensional shift allows latch-up suppression without enlarging chip area

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If a barrier layer with gradient doping profile is introduced to suppress electron carrier injection, then latch-up effects are reduced, but device complexity increases

Engineering Contradiction:
Improvelatch-up suppressionVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The barrier layer employs a gradient doping profile where the dopant concentration varies continuously from the substrate interface to the epitaxial layer interface. This parameter variation creates an electric field that suppresses electron carrier injection and latch-up effects while maintaining a relatively simple single-layer structure

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The barrier layer is formed as a composite structure combining regions of different doping concentrations within a single continuous layer, creating a gradient profile that provides enhanced latch-up suppression functionality without requiring multiple discrete layers

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The structure effectively reduces latch-up effects by suppressing electron carrier injection, maintaining device performance while keeping chip size compact.

Implementation Method 1

the barrier layer has a higher dopant concentration level at a middle portion of the barrier layer and has a lower dopant concentration level at a top of the barrier layer and at a bottom of the barrier layer

Methodology Applied
Scientific EffectGradient doping profile:

Implementation Method 2

to suppress electron carrier injection and reduce lateral parasitic current

Methodology Applied
Scientific EffectCarrier suppression:

Implementation Method 3

at least one isolation structure formed in the doped regions to separate two of the doped regions

Methodology Applied
Scientific EffectPhysical isolation: Physical Containment

Data Source

PatentUS20250338582A1Semiconductor structure and method for manufacturing the same
Publication Date: 2025.10.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250338582A1 patent drawing
  • US20250338582A1 patent drawing
  • US20250338582A1 patent drawing

AI summary

A semiconductor structure is provided. The semiconductor structure includes a substrate with a first dopant concentration, a barrier layer, an epitaxial layer with a second dopant concentration and a plurality of doped regions. The barrier layer is formed on the substrate and has a first conductivity type with a gradient doping profile. The barrier layer has a higher dopant concentration level at a middle portion of the barrier layer and has a lower dopant concentration level at a top of the barrier layer and at a bottom of the barrier layer. The epitaxial layer is formed on the barrier layer. The plurality of doped regions are formed on the epitaxial layer. The higher dopant concentration level is greater than the first dopant concentration and is also greater than the second dopant concentration.