Gradient BPSG Stack Sidewall Tapering Control
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Solution Overview
Problem
The formation of openings in semiconductor substrates for memory devices often results in tapering, necking, or bending of sidewalls due to varying etch rates of chemical compounds, leading to reduced electrical isolation, capacitance, and increased risk of short circuits.
Innovation Solution
A gradient borophosphosilicate glass (BPSG) stack with varying concentrations of boron and phosphorous is formed on the semiconductor substrate to control the etch rate and reduce tapering, necking, or bending of sidewalls during the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional etching processes are used to form openings in semiconductor substrates, then the etching process can be completed, but tapering, necking, or bending of sidewalls occurs due to varying etch rates of chemical compounds
Solution Approach 1:
The patent applies local quality by creating a gradient BPSG stack where the boron and phosphorous concentrations vary spatially through the layer thickness. This gradient structure provides different etch resistance at different depths, with the top portion having different composition than the bottom portion, allowing the etch rate to be locally optimized at each depth to maintain vertical sidewalls and prevent tapering
Solution Approach 2:
The patent changes the chemical composition parameters of the BPSG stack by creating a gradient in boron and phosphorous concentrations. This parameter change transforms the uniform etch resistance into a depth-dependent etch resistance profile, where the etch rate varies systematically through the layer to compensate for tapering effects and maintain consistent sidewall width
2Productivity
If conventional etching processes are used, then openings can be formed, but electrical isolation is reduced and capacitance decreases due to sidewall tapering and necking
Solution Approach 1:
The gradient BPSG stack provides locally optimized etch resistance at different depths, ensuring that the etching process maintains uniform sidewall width throughout the opening depth. This local quality control prevents necking that would reduce capacitor surface area and maintain electrical isolation by preventing unintended connections between adjacent structures
Solution Approach 2:
The patent uses a composite BPSG stack with graded composition rather than a uniform material. The composite structure combines different ratios of boron and phosphorous compounds in a gradient fashion, creating a material system with depth-dependent properties that simultaneously achieves clean opening formation and maintains structural integrity for electrical isolation and capacitance
3Productivity
If conventional etching processes are used, then openings can be formed, but the risk of short circuits increases due to sidewall bending and necking
Solution Approach 1:
The gradient BPSG stack provides depth-dependent etch resistance that maintains vertical sidewall geometry throughout the etching process. This local quality control prevents sidewall bending and necking that could create weak points or unintended conductive paths, thereby reducing short circuit risk while maintaining productive opening formation
Solution Approach 2:
The gradient BPSG stack acts as a preventive measure by being deposited beforehand with a composition profile designed to counteract expected etching effects. The varying concentrations of boron and phosphorous are predetermined to provide appropriate etch resistance at each depth, cushioning against the development of tapering, necking, or bending that would lead to short circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The controlled etch rate and reduced tapering enhance the surface area of capacitors, increase capacitance, and minimize the risk of short circuits by maintaining a consistent sidewall width and reducing the occurrence of necking or bending.
Implementation Method 1
A gradient borophosphosilicate glass (BPSG) stack with varying concentrations of boron and phosphorous is formed on the semiconductor substrate to control the etch rate and reduce tapering, necking, or bending of sidewalls during the etching process
Data Source
AI summary
Methods, apparatuses, and systems related to reduction of tapering on a sidewall of an opening are described. An example method includes forming a silicate material comprising a gradient borophosphosilicate glass (BPSG) stack on a semiconductor structure. The example method further includes etching a portion of the silicate material to form an opening within the silicate material having sidewalls, wherein the gradient BSPG stack comprises varying concentrations of boron and phosphorous to reduce tapering of the sidewalls in response to the etching.