Gradient-Hardness Bump Structure for Chip Bonding Stress
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Solution Overview
Problem
The shrinkage of bump size in chip bonding leads to increased deformation and potential damage due to greater force applied per unit area, which existing technologies fail to adequately address.
Innovation Solution
A bump structure comprising multiple layers with different hardness, where the first bump layer buffers the force and the second bump layer with higher hardness absorbs it, preventing deformation and damage by eliminating force transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If bump size is reduced to meet process requirements and cost constraints, then manufacturing precision and productivity are improved, but the bump structure becomes more susceptible to deformation and damage under stress
Solution Approach 1:
The bump structure is divided into multiple layers (first bump layer, second bump layer, and third bump layer) with different hardness values. This segmentation allows each layer to perform different functions: the softer first layer absorbs stress, the harder second layer provides structural support, and the third layer provides additional protection, collectively preventing deformation while maintaining small size
Solution Approach 2:
Different regions of the bump structure are assigned different hardness properties. The first bump layer has lower hardness (30-50 HV) for stress absorption, while the second and third layers have higher hardness (50-70 HV and 70-90 HV respectively) for structural integrity. This local differentiation of material properties enables the structure to simultaneously achieve stress resistance and dimensional stability
2Device complexity
If a single-layer bump structure is used, then device complexity is reduced, but the structure cannot effectively cancel out applied forces and prevent damage
Solution Approach 1:
The bump structure uses composite material design with multiple layers of the same conductive material (such as copper, aluminum, or gold) but with different hardness values achieved through controlled crystal grain sizes. This composite approach maintains electrical conductivity while providing mechanical protection against force-induced damage through the gradient hardness structure
Solution Approach 2:
The first bump layer with lower hardness is positioned at the bottom to beforehand cushion and absorb stress during the bonding process. This pre-positioned cushioning layer prevents force from being directly transmitted to the chip, eliminating the need for complex external protection mechanisms
Data Source
AI summary
The present application discloses a bump structure and a manufacturing method thereof. The bump structure comprises a first bump layer disposed on a chip and a second bump layer disposed on the first bump layer, and the hardness of the first and second bump layers are different, and both materials of the first and second bump layers are the same conductive material. Thus, when the chip is connected with a substrate through the bump structure and a force applied to the bump structure, it is not easily to cause that the bump structure makes a damage on the chip, and the bump structure according to the present invention is to enhance the structure characteristic and prevented from damaging.