Gradient Grain Size Semiconductor Layer for Photoelectric Conversion
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Solution Overview
Problem
Existing photoelectric conversion devices face challenges in improving efficiency due to the formation of cracks in semiconductor layers with larger crystal grains, which hinder effective photoelectric conversion.
Innovation Solution
A photoelectric conversion device is designed with a first polycrystalline semiconductor layer having larger average grain diameters on the surface portions compared to the central portion, reducing stress and enhancing charge mobility by gradient grain size distribution, and a second semiconductor layer forming a pn junction to improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of crystal grains of the semiconductor layer is increased to improve photoelectric conversion efficiency, then photoelectric conversion efficiency is improved, but cracks easily appear on the semiconductor layer due to thermal stress
Solution Approach 1:
The patent applies local quality by creating a gradient grain size distribution within the semiconductor layer. The central portion has larger crystal grains (average diameter 10-50 μm) for high photoelectric conversion efficiency, while the surface portion has smaller crystal grains (average diameter 1-10 μm) for reduced thermal stress and improved crack resistance. This spatial variation in grain size allows different regions to fulfill different functional requirements simultaneously.
Solution Approach 2:
The patent changes the physical parameter of crystal grain size across the semiconductor layer thickness. By controlling the average grain diameter to be larger in the central portion and smaller in the surface portion, the patent optimizes both photoelectric conversion efficiency (requiring large grains) and mechanical reliability (requiring small grains for stress distribution). This parameter gradient is achieved through specific deposition conditions and heat treatment processes.
2Power
If the size of crystal grains of the semiconductor layer is increased to improve photoelectric conversion efficiency, then charge mobility is improved, but thermal stress causes cracks that reduce efficiency
Solution Approach 1:
The patent creates different grain sizes in different regions: the central portion has large grains (10-50 μm) that provide high charge mobility and low recombination, while the surface portion has small grains (1-10 μm) that distribute thermal stress uniformly. This local differentiation allows the semiconductor layer to simultaneously achieve high power conversion and resistance to thermal stress.
Solution Approach 2:
The patent prepares the semiconductor layer structure in advance to cushion against thermal stress. By forming smaller grains in the surface portion before device operation, the structure is pre-configured to distribute and absorb thermal stress during subsequent heating processes, preventing crack formation that would otherwise occur in uniformly large-grained structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances photoelectric conversion efficiency by reducing strain and crack occurrence while improving charge mobility and adhesion, leading to improved performance.
Implementation Method 1
a second semiconductor layer disposed on/above the first semiconductor layer and forming a pn junction with the first semiconductor layer
Implementation Method 2
photoelectric conversion device including a polycrystalline semiconductor
Implementation Method 3
cracks easily appear on the semiconductor layer due to thermal stress or the like
Data Source
AI summary
In order to improve the photoelectric conversion efficiency of a photoelectric conversion device, this photoelectric conversion device is provided with an electrode layer, a first semiconductor layer that is positioned on the electrode layer and contains a polycrystalline semiconductor, and a second semiconductor layer that is positioned on/above the first semiconductor layer and forms a p-n junction with the first semiconductor layer, and an average grain diameter of crystal grains in the first semiconductor layer is larger near the surface on the electrode layer side of the first semiconductor layer than the center of the first semiconductor layer in a thickness direction of the first semiconductor layer. Furthermore, the average grain diameter of the crystal grains in the first semiconductor layer is larger in a surface portion on the second semiconductor layer side of the first semiconductor layer than in the central portion.