Gradient Porous Interlayer Insulation for Semiconductor Wiring
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Solution Overview
Problem
The increase in integration density of semiconductor devices leads to reliability issues due to RC delay and potential collapse of interconnection lines, particularly when using low-k dielectric materials with air gaps, which can result in either collapse or insufficient insulation.
Innovation Solution
A semiconductor device structure featuring a substrate with wiring lines, an interlayer insulating structure comprising a non-porous layer, a pore-containing layer with monotonically increasing pore volumes, and an air gap, covered by a silicon oxycarbide-based layer, along with a barrier and etch stop layer, to prevent collapse and reduce RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If low-k dielectric material with air gap is used to reduce RC delay, then signal transmission speed is improved, but wiring line collapse occurs
Solution Approach 1:
The patent applies local quality by creating a gradient pore structure where pore volumes increase monotonically from the substrate toward the air gap. This gradual transition in porosity provides localized mechanical support where needed (near the substrate) while maintaining low-k dielectric properties (near the air gap), preventing wiring line collapse in critical areas while preserving signal transmission speed benefits.
Solution Approach 2:
The patent utilizes porous materials by incorporating a pore-containing layer with controlled pore volumes within the interlayer insulating structure. The pores are strategically distributed to provide mechanical reinforcement to the interlayer insulating structure, preventing wiring line collapse while maintaining the low-k dielectric properties needed for reduced RC delay.
2Speed
If air gap is formed to reduce RC delay, then signal transmission speed is improved, but insulating material may be absent leading to low reliability
Solution Approach 1:
The patent applies local quality by creating distinct regions within the interlayer insulating structure: a non-porous layer near the substrate providing reliable insulation, a pore-containing layer with gradient porosity providing mechanical support, and an air gap region providing maximum RC delay reduction. Each region is optimized for its specific function while working together as a unified structure.
Solution Approach 2:
The patent employs composite materials by combining non-porous dielectric material, porous dielectric material with gradient pore structure, and air gap within a single interlayer insulating structure. This composite approach allows the structure to simultaneously provide mechanical support, reliable insulation, and low-k dielectric properties for reduced RC delay.
3Productivity
If integration density is increased to improve device performance, then productivity is improved, but RC delay and wiring collapse increase
Solution Approach 1:
The patent utilizes porous materials with gradient pore structure to enable higher integration density while maintaining reliability. The controlled porosity provides mechanical support to prevent wiring collapse and maintains low-k dielectric properties to reduce RC delay, allowing the device to achieve higher integration density without sacrificing reliability.
Solution Approach 2:
The patent employs composite interlayer insulating structure combining non-porous, porous, and air gap regions to enable higher integration density. The composite structure provides distributed mechanical support and optimized electrical properties throughout the interconnection architecture, allowing increased element density while maintaining wiring integrity and signal transmission quality.
Data Source
AI summary
A semiconductor device can include wiring lines on a substrate and an interlayer insulating structure, between ones of the wiring lines. The wiring lines can include a pore-containing layer that includes a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines.