Gradient Spacer Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The challenge in semiconductor technology is the difficulty in reducing the size of horizontal semiconductor devices, which hinders the increase in integration density and leads to increased parasitic capacitance, affecting the performance of vertical semiconductor devices.
Innovation Solution
A method for manufacturing a semiconductor device involves forming spacers with varying thickness around the channel region between the gate stack and source/drain regions, using oxidation treatment and etching, to reduce parasitic capacitance and improve switching performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of vertical semiconductor device is reduced to increase integration density, then integration density is improved, but parasitic capacitance increases
Solution Approach 1:
The spacer structure implements local quality by having different thicknesses at different locations: thicker at the bottom (near source/drain regions) and thinner at the top (near gate electrode). This gradient thickness distribution optimizes the local electrical characteristics, providing better parasitic capacitance reduction where needed while maintaining appropriate spacing elsewhere, thus resolving the contradiction between high integration density and low parasitic capacitance.
Solution Approach 2:
The invention changes the geometric parameter of the spacer from uniform thickness to gradient thickness. By controlling the thickness parameter to vary along the vertical direction, the spacer achieves optimized electrical performance that reduces parasitic capacitance between gate and source/drain regions, enabling higher integration density without the harmful effect of increased parasitic capacitance.
2Ease of manufacture
If uniform thickness spacer is used, then manufacturing process is simple, but parasitic capacitance reduction is insufficient
Solution Approach 1:
The spacer structure is formed as a preliminary action before final device operation, with its gradient thickness profile pre-designed to achieve optimal parasitic capacitance reduction. The oxidation and etching processes are performed in advance to create the desired thickness distribution, enabling effective capacitance reduction without complicating subsequent manufacturing steps.
Solution Approach 2:
The spacer acts as an intermediary structure between the gate electrode and source/drain regions. By introducing this intermediate element with carefully controlled gradient thickness, the invention mediates the electrical interaction between gate and source/drain, reducing parasitic capacitance while maintaining a relatively simple manufacturing process using standard oxidation and etching techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance, enhancing the switching performance of the semiconductor device by increasing the distance between the gate stack and source/drain regions, thereby accelerating current build-up and improving integration density.
Implementation Method 1
forming spacers around an outer periphery of the channel region, respectively at set positions of the substrate and the second material layer
Data Source
AI summary
The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The method includes: forming a first material layer and a second material layer sequentially on a substrate; defining an active region of the semiconductor device on the substrate, the first material layer and the second material layer, wherein the active region includes a channel region; forming spacers around an outer periphery of the channel region, respectively at set positions of the substrate and the second material layer; forming a first source/drain region and a second source/drain region on the substrate and the second material layer respectively; and forming a gate stack around the outer periphery of the channel region; wherein the spacers each have a thickness varying in a direction perpendicular to a direction from the first source/drain region pointing to the second source/drain region.