Graduated Gate Metal Work Function for High Voltage Transistors

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Solution Overview

Problem

Current semiconductor technologies face challenges in scaling transistors for System on a Chip (SoC) applications, as lateral scaling reduces high voltage operating windows and increases peak electric fields, making it difficult to support both low leakage and high voltage devices without hindering logic transistor operation.

Innovation Solution

The implementation of a gate metal with a laterally graduated work function, where the work function is modulated between the source and drain edges by varying the thickness or composition of the gate metal, allowing for improved high voltage performance while maintaining compatibility with low voltage logic transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If lateral scaling is applied to reduce transistor size for Moore's Law, then area scaling and performance are improved, but peak electric field increases and high voltage operating window decreases

Engineering Contradiction:
Improvetransistor areaVSAvoidpeak electric field
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The gate electrode is designed with spatially varying properties: a first gate electrode material with a first work function is used near the source region, and a second gate electrode material with a second work function is used near the drain region. This local differentiation allows the electric field to be modulated in specific areas, reducing the peak electric field near the drain while maintaining effective gate control, thus resolving the contradiction between lateral scaling and peak electric field reduction.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If lateral scaling is applied to reduce transistor size, then area scaling is improved, but high voltage operation capability deteriorates

Engineering Contradiction:
Improvetransistor areaVSAvoidhigh voltage operation capability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

Different gate electrode materials with different work functions are employed at different lateral positions: the first material near the source and the second material near the drain. This spatial variation in gate properties enables the transistor to maintain high voltage operation capability by reducing peak electric field effects, while still achieving area scaling through reduced gate length.

Inventive Principle:
Principle #3Local quality

3Reliability

If gate electrode work function is modulated to reduce peak electric field, then high voltage performance is improved, but integration with low voltage logic transistors becomes more difficult

Engineering Contradiction:
Improvehigh voltage performanceVSAvoidintegration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate electrode is segmented into different material regions: a first gate electrode material near the source and a second gate electrode material near the drain. This segmentation allows each region to be optimized for its specific function while maintaining a unified transistor structure that can be integrated with standard low voltage logic transistors using conventional fabrication processes.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP3183752B1Transistor gate metal with laterally graduated work function
Publication Date: 2021.07.21 INTEL CORP
  • EP3183752B1 patent drawingFigure 1A~1B
  • EP3183752B1 patent drawingFigure 2A~2B
  • EP3183752B1 patent drawingFigure 3A~3B

AI summary

Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.