Granular Dynamic Test System With Ultra-Fast Interface
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Solution Overview
Problem
Conventional testing approaches for semiconductor devices are inefficient and costly due to the need for computationally intensive and time-consuming processes, particularly in System on Chip (SoC) designs, where traditional scan-based tests struggle with communication and parallel testing across multiple partitions, leading to complex and costly test environments.
Innovation Solution
A granular dynamic test system with an Ultra-Fast Interface (UFI) that enables flexible and concurrent testing across multiple partitions by using a centralized test controller and interface that operates at different clock speeds, allowing for efficient communication and management of test operations, including Automatic Test Pattern Generation (ATPG) and Memory Built In Self Test (MBIST), through a standardized test interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional scan-based testing is used for multiple test partitions, then testing coverage is achieved, but test time becomes excessively long and computational resources are overwhelmed
Solution Approach 1:
The system divides the chip into multiple independent test partitions, each with its own scan chains and test controller. This segmentation allows parallel testing of different partitions simultaneously, reducing overall test time while maintaining comprehensive coverage. Each partition can be tested independently with dedicated resources.
Solution Approach 2:
The patent introduces a hierarchical testing architecture that adds temporal and spatial dimensions to traditional testing. Multiple test partitions operate in parallel (spatial dimension), and the system coordinates testing across different clock domains (temporal dimension), transforming sequential testing into concurrent multi-dimensional testing.
2Productivity
If test clock frequency is increased to reduce test time, then testing speed improves, but signal integrity and communication reliability deteriorate
Solution Approach 1:
The system segments the clocking architecture into multiple independent clock domains, each optimized for its specific test partition. This allows each partition to operate at its optimal clock frequency without interfering with others, maintaining signal integrity while achieving high overall testing speed through parallel operation.
Solution Approach 2:
The patent dynamically adjusts clock frequencies for different test partitions based on their specific requirements. Each partition can operate at different clock speeds optimized for its characteristics, rather than using a single high frequency for all partitions, thus maintaining signal integrity while maximizing testing productivity.
3Adaptability or versatility
If conventional test architecture is used to support multiple test vector types, then testing flexibility is limited, but system complexity and coordination requirements increase significantly
Solution Approach 1:
The system segments test vector types and test partitions, allowing each partition to be optimized for specific test vector types (e.g., memory partitions for MBIST, logic partitions for scan testing). This segmentation enables flexible mixing of different test types across partitions without requiring complex coordination for homogeneous testing.
Solution Approach 2:
The test architecture provides universal support for multiple test vector types across all partitions through standardized interfaces and controllers. Each partition controller can handle various test types (scan, memory, BIST) independently, enabling flexible test mixing without increasing overall system complexity.
4Productivity
If parallel testing of multiple partitions is attempted using conventional methods, then test efficiency improves, but coordination complexity and resource requirements become unmanageable
Solution Approach 1:
The system segments control functions by assigning dedicated partition controllers to each test partition. Each controller independently manages its partition's test operations, eliminating the need for complex centralized coordination. This segmentation enables parallel testing while keeping coordination complexity localized to each partition.
Solution Approach 2:
The patent introduces a hierarchical control structure that adds a spatial dimension to test coordination. Instead of single-dimensional sequential control, the system uses multi-dimensional parallel control across independent partitions, each operating in its own control domain but synchronized through standardized interfaces.
Data Source
AI summary
In one embodiments, a system comprises: a plurality of scan test chains configured to perform test operations at a first clock speed; a central test controller for controlling testing by the scan test chains; and an interface configured to generate instructions to direct central test controller. The interface communicates with the centralized test controller at the first clock speed and an external scan input at a second clock speed. The second clock speed can be faster than the first clock speed. The instructions communicated to the central controller can be directions associated with sequential scan compression/decompression operations. In one exemplary implementation, the interface further comprise a mode state machine used to generate the mode control instructions and a test register state machine that generate test state control instructions, wherein the test mode control instructions and the test state control instructions direct operations of the centralized test controller.