Graph-Based Hardware Debugger for Assertion-Driven Design Verification
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Solution Overview
Problem
Current hardware design techniques are inefficient due to extensive validation and verification processes, and they fail to effectively address data flow control and protocol logic during the design process, leading to increased time and complexity.
Innovation Solution
A debugger system and method utilizing a common hardware database that translates hardware designs into a graph-based representation, allowing for conditional display of hardware design constructs based on assertion conditions, and uses signal dumps to determine corresponding values, thereby facilitating error identification and visualization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current hardware description languages are used for validation and verification, then hardware design can be performed, but the process becomes time-consuming and complex
Solution Approach 1:
The patent applies preliminary action by performing validation and verification activities during the hardware design process itself, rather than as separate post-design steps. The hardware description language includes built-in verification constructs that allow designers to check design correctness, data flow control, and protocol logic adherence while the design is being created, thus preventing errors before they propagate through the design schedule.
Solution Approach 2:
The patent implements feedback mechanisms through the hardware description language that provide real-time validation and verification information during design. The language includes constructs that automatically check design properties, data flow correctness, and protocol compliance, providing immediate feedback to designers about potential errors or violations, allowing for rapid correction without extensive manual verification cycles.
2Adaptability or versatility
If current hardware description languages are used, then hardware design can proceed, but data flow control and protocol logic are not effectively addressed
Solution Approach 1:
The patent applies universality by designing a hardware description language that integrates multiple functions into a unified framework. The language simultaneously handles structural description, data flow control, protocol logic verification, and validation activities through integrated constructs. This multi-functional approach allows designers to address data flow control and protocol logic within the same language framework rather than requiring separate tools or methodologies.
Solution Approach 2:
The patent utilizes parameter changes by introducing new language constructs and syntax elements specifically designed for data flow control and protocol logic. These parameter extensions to the hardware description language enable precise specification and verification of data flow behaviors, control signals, and protocol compliance rules, transforming the language's capabilities to effectively handle these previously inadequate areas.
3Reliability
If extensive validation and verification processes are used, then design correctness can be ensured, but the overall design process complexity increases
Solution Approach 1:
The patent applies merging by combining validation and verification processes with the hardware design process itself. Rather than treating these as separate, complex external processes, the language integrates verification constructs directly into the design description, allowing validation activities to be performed concurrently with design development. This merging reduces overall process complexity while maintaining design correctness.
Solution Approach 2:
The patent implements self-service through automated validation and verification constructs within the hardware description language that enable the design process to validate and verify itself. The language includes built-in mechanisms for checking design correctness, data flow control, and protocol logic without requiring extensive external verification tools or manual processes, thus reducing overall process complexity while ensuring design correctness.
Data Source
AI summary
A hardware model database is identified which stores a graph-based common representation of a hardware design that includes hardware module nodes each representative of a unique module of the hardware design and associated with one or more instances of the unique module. Additionally, a signal dump resulting from a simulation of a logic code model of the hardware design is identified. Each instance of each unique module is identified using the hardware model database, and for each assertion condition included therein, a corresponding value for the assertion condition is determined from the signal dump. Further, a construct of the hardware design corresponding to each instance of each unique module is conditionally displayed by a debugger application, based on the determined values of the corresponding assertion conditions included in the instance of the unique module.