Graph Structure Cache for Neural Network Memory Optimization

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Solution Overview

Problem

Graph neural networks (GNNs) face inefficiencies in memory utilization due to the large memory requirements of adjacency matrices for representing graph structures, especially for large graphs.

Innovation Solution

A graph structure cache, utilizing a content addressable memory (CAM) array and a random-access memory (RAM) array, is introduced to efficiently store and retrieve graph structures, reducing memory usage and enhancing processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If adjacency matrices are used to represent graph structures, then graph structures can be stored and accessed, but memory consumption increases significantly for large graphs

Engineering Contradiction:
Improvegraph structure storage and accessVSAvoidmemory consumption
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The patent segments the graph structure representation into two separate components: a CAM array that stores node identifiers and their binary representations, and a RAM array that stores the actual graph data. This segmentation allows efficient addressing and retrieval while reducing the memory footprint compared to a complete adjacency matrix representation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a traditional two-dimensional adjacency matrix to a multi-dimensional storage structure using CAM and RAM arrays. The CAM array provides binary content-addressable access, adding a new dimension of addressing efficiency, while the RAM array provides sequential access for data retrieval. This dimensional transformation enables O(1) lookup time while reducing space complexity from O(V²) to O(V+E).

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If larger memory is allocated to store graph structures, then more graphs can be represented, but processing efficiency decreases due to increased memory access time

Engineering Contradiction:
Improvegraph representation capacityVSAvoidprocessing efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent performs preliminary action by pre-computing and storing the binary representations of node identifiers in the CAM array before graph processing begins. This pre-processing enables rapid lookup during graph operations, as the CAM array can directly match incoming node identifiers against the pre-stored binary patterns without requiring complex computation during the actual graph processing phase.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The CAM array serves as an intermediary between the input node identifier and the RAM array containing the actual graph data. When a node identifier needs to be processed, the CAM array first performs rapid binary matching to locate the corresponding entry, then the RAM array retrieves the actual data. This intermediary structure enables efficient navigation through large graphs by decoupling the lookup operation from the data retrieval operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12339785B2Graph cache
Publication Date: 2025.06.24 HEWLETT PACKARD ENTERPRISE DEV LP
  • US12339785B2 patent drawing
  • US12339785B2 patent drawing
  • US12339785B2 patent drawing

AI summary

A cache is used for efficiently storing a graph structure. The graph cache may be used in a computing system to accelerate processing of a graph by a graph neural network, and is different than a general-purpose memory of the computing system. Embeddings for the nodes of a graph are stored in the memory of the computing system, while the structure of the graph is stored in the graph cache. The graph cache may include a content addressable memory array, which may be suitable for efficiently representing a graph structure.