Graph Compilation with Multi-Access Instructions and Memory Bank Allocation
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Solution Overview
Problem
The architectural constraints of memory devices, which prevent simultaneous access to different memory locations within the same bank, conflict with the implementation of multi-access instructions in processor systems, necessitating a method to allocate data elements across different memory banks while ensuring that different load or store operations do not access the same bank in the same instruction.
Innovation Solution
A computer-implemented method for generating an executable program that includes multi-access instructions, where data elements are allocated to different memory banks, and the compilation process ensures that these instructions do not access the same memory bank simultaneously, using constraints such as alignment and storage in specific subsets of memory banks, including interleaved memory, to manage memory access efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-access instructions are implemented to perform multiple load and store operations in a single instruction, then instruction efficiency and productivity are improved, but memory bank access conflicts occur when different operations access the same bank simultaneously
Solution Approach 1:
The memory system is divided into multiple independent memory banks, each capable of handling access operations independently. This segmentation allows multi-access instructions to perform multiple load and store operations simultaneously by directing different operations to different banks, thereby maintaining instruction efficiency while preventing access conflicts.
Solution Approach 2:
Different memory banks are allocated for different data elements based on their access patterns and requirements. The compiler analyzes the program and assigns data elements to specific banks locally, ensuring that operations within a single instruction access different banks. This local allocation strategy resolves the contradiction by making each bank's access pattern independent and conflict-free.
2Reliability
If data elements are allocated to different memory banks to avoid access conflicts, then memory access reliability is improved, but device complexity increases due to the need for bank allocation management
Solution Approach 1:
The compiler automatically performs the complex task of analyzing the program's memory access patterns and allocating data elements to appropriate memory banks. This self-service approach eliminates the need for manual allocation management by developers, reducing the perceived complexity while maintaining reliable memory access. The compiler's automatic allocation system handles the complexity internally, presenting a simple interface to users.
3Device complexity
If the memory architecture prevents simultaneous access to different memory locations within the same bank, then hardware simplicity is maintained, but instruction performance deteriorates when multiple operations need to access the same bank
Solution Approach 1:
The memory system is divided into multiple independent memory banks, each capable of handling access operations independently. This segmentation allows multi-access instructions to perform multiple load and store operations simultaneously by directing different operations to different banks, thereby maintaining instruction efficiency while preventing access conflicts.
Solution Approach 2:
The solution moves from a single-dimension memory access model (one bank at a time) to a multi-dimensional model where multiple banks can be accessed in parallel. By adding the bank dimension, the system achieves simultaneous access capability without complicating the internal architecture of individual banks, thus maintaining hardware simplicity while improving performance.
Data Source
AI summary
A method for generating an executable program to run on one or more processor modules. The method comprises: receiving a graph comprising a plurality of data nodes, compute vertices and edges; and compiling the graph into an executable program including one or more types of multi-access instruction each of which performs at least two memory access (load and/or store) operations in a single instruction. The memory on each processor module comprises multiple memory banks whereby the same bank cannot be accessed by different load or store operations in the same instruction. The compilation comprises assigning instances of the multi-access instructions to implement at least some of the graph edges, and allocating the data to memory addresses within different ones of the banks. The allocating is performed subject to one or more constraints, including at least that different load/store operations should not access the same memory bank in the same instruction.