Graph Conversion for Tile-Mapping in Parallel Processing

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Solution Overview

Problem

Existing tools for parallel processing systems only balance processing and memory burdens evenly across tiles without considering the meaning or dimensionality of data, leading to inefficient data allocation and processing.

Innovation Solution

A computer-implemented method generates an executable program by using an API to convert a graph-based program into a tile-mapping format, allocating data nodes and vertices based on compute vertex types, which determines optimal memory allocation functions for each type of computation, ensuring data is stored and processed efficiently across tiles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is allocated evenly across tiles without considering data meaning, then processing burden is balanced, but memory access efficiency deteriorates

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidmemory access time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies local quality by allocating data to tiles based on the specific access patterns and computational requirements of different data types. Instead of uniform allocation, the system identifies which tiles will frequently access which data and places that data on those specific tiles, making the allocation non-uniform but optimized for local access efficiency.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system performs preliminary analysis of the computation graph to identify access patterns before execution. By pre-determining which tiles will access which data during computation, the system can pre-allocate data to appropriate tiles before the computational workload begins, avoiding runtime data movement and improving access efficiency.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If data is placed on different tiles for parallel processing, then processing capacity increases, but communication overhead between tiles increases

Engineering Contradiction:
Improveparallel processing capacityVSAvoidcommunication energy
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent merges related data and computations onto the same tile when possible. By analyzing the computation graph, the system identifies data that is frequently accessed together or by the same computational units and co-locates them on the same tile, reducing the need for inter-tile communication and the associated energy overhead.

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If manual allocation of data to tiles is performed, then allocation precision can be optimized, but system complexity increases

Engineering Contradiction:
Improvedata allocation precisionVSAvoidallocation system complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The system employs automated analysis of computation graphs to self-determine optimal data allocation strategies. Rather than requiring manual configuration, the system automatically identifies access patterns, data dependencies, and computational requirements, then generates allocation decisions autonomously, achieving high precision without increasing user-facing complexity.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system uses feedback from analyzing actual or predicted computation workloads to refine allocation decisions. By examining the computation graph and identifying access patterns, the system continuously optimizes allocation based on feedback about how data will actually be used, achieving high precision allocation adaptively.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11630986B2Graph conversion method
Publication Date: 2023.04.18 GRAPHCORE LTD
  • US11630986B2 patent drawing
  • US11630986B2 patent drawing
  • US11630986B2 patent drawing

AI summary

A method for generating an executable program to run on a system of one or more processor chips each comprising a plurality of tiles. The method comprises: receiving a graph comprising a plurality of data nodes, compute vertices and directional edges, wherein the graph is received in a first graph format that does not specify which data nodes and vertices are allocated to which of the tiles; and generating an application programming interface, API, for converting the graph, to determine a tile-mapping allocating the data nodes and vertices amongst the tiles. The generating of the API comprises searching the graph to identify compute vertices which match any of a predetermined set of one or more compute vertex types. The API is then called to convert the graph to a second graph format that includes the tile-mapping, including the allocation by the assigned memory allocation functions.