Graph Edge Pruning in Minor Embeddings to Reduce Physical Qubits

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Solution Overview

Problem

Current Quantum Annealer hardware requires excessive qubits due to NP-hard minor-embedding problems, leading to inefficient resource usage and suboptimal solution quality, as existing heuristics fail to provide exact mappings in practical time.

Innovation Solution

A post-processing approach that ranks and removes edges based on entanglement coefficients using Tarjan's algorithm to minimize the number of qubits needed, ensuring fewer qubits are used while maintaining solution quality for less sensitive QUBO problems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If heuristics are used for minor-embedding, then practical running time is reduced, but solution quality deteriorates and more qubits are used than needed

Engineering Contradiction:
Improverunning timeVSAvoidembedding quality
Core Design Contradiction:
Loss of timeVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by performing edge removal operations before the final embedding is executed. The method pre-processes the graph by identifying and removing unnecessary edges based on entanglement coefficients, thereby preparing an optimized embedding that reduces qubit requirements while maintaining solution quality. This preliminary optimization prevents the need for post-processing corrections and ensures efficient resource utilization from the start.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If NP-hard minor-embedding problem is solved exactly, then optimal qubit mapping is achieved, but computational complexity becomes intractable

Engineering Contradiction:
Improveembedding optimalityVSAvoidcomputational complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies the extraction principle by removing unnecessary edges from the graph based on entanglement coefficients. By extracting and eliminating edges that contribute minimally to the overall entanglement structure, the method simplifies the embedding problem while preserving the essential quantum correlations needed for accurate QUBO solution. This reduction in graph complexity makes the embedding tractable without sacrificing optimality.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies parameter changes by utilizing entanglement coefficients as a metric to guide edge removal decisions. By changing the parameter space from considering all possible edges to selectively removing edges below certain entanglement thresholds, the method transforms the intractable NP-hard problem into a manageable optimization task that maintains solution quality while reducing computational burden.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If fully connected qubit architecture is implemented, then any input graph can be accommodated, but hardware complexity and resource requirements escalate exponentially

Engineering Contradiction:
Improvegraph accommodation capabilityVSAvoidhardware complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-processing the input graph to identify and remove edges that would require excessive hardware connections. By performing edge removal based on entanglement coefficients before mapping to physical qubits, the method prepares an optimized graph representation that reduces the connectivity requirements of the quantum hardware while maintaining the ability to solve the original QUBO problem effectively.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250292139A1Minor embedding post-processing to reduce physical qubits
Publication Date: 2025.09.18 DELL PROD LP
  • US20250292139A1 patent drawing
  • US20250292139A1 patent drawing
  • US20250292139A1 patent drawing

AI summary

One example method includes ranking all edges e of a graph G that was obtained using a minor embedding process performed on a graph topology Q, and the ranked edges are included in a list R, creating a graph G′ by copying G, and for each of the edges e, performing, for as long as a stop criterion has not been met, operations that include: identifying nodes and edges in the graph G′, removing, from the graph G′, any edges that meet an adjacency criterion, and placing the removed edges in a set B′ of edges, removing, from the list R, all edges of the B′ of edges, and removing, from the graph G′, the edge e.