Graph Embedding in 3D Lattice for Quantum Processors

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Solution Overview

Problem

Current graph embedding techniques are inefficient for large graphs, as they rely on planarization, leading to longer edge lengths and greater surface area, and fail to optimize resource usage and path lengths effectively.

Innovation Solution

The method involves embedding a source graph into a target graph by forming islands and inter-island bridges in a lattice structure, optimizing the embedding by reducing vertices, edges, and area, and modifying the configuration and orientation of islands and bridges.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If planarization is used for graph embedding, then the graph can be embedded in a 2D plane, but edge lengths and surface area increase significantly

Engineering Contradiction:
Improveembedding feasibilityVSAvoidedge length
Core Design Contradiction:
Ease of manufactureVSLength of stationary object

Solution Approach 1:

The patent transitions from 2D planar embedding to 3D lattice embedding, allowing graphs to be represented in three-dimensional space. This dimensional change enables shorter edge lengths and more efficient routing by utilizing the z-dimension, thereby resolving the contradiction between embedding feasibility and edge length minimization

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If planarization is used for graph embedding, then the graph can be embedded in a 2D plane, but the surface area required increases

Engineering Contradiction:
Improveembedding feasibilityVSAvoidsurface area
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

By moving from 2D to 3D embedding space, the patent reduces the surface area footprint. The lattice structure in three dimensions allows for more compact graph representations, decreasing the required surface area while maintaining embedding feasibility

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Device complexity

If traditional embedding techniques are used, then implementation is simpler, but resource usage efficiency decreases

Engineering Contradiction:
Improveembedding complexityVSAvoidresource usage efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent introduces dynamic optimization of the lattice embedding configuration, where the embedding can be adjusted and optimized for specific graph types and requirements. This dynamic approach improves resource usage efficiency by adapting the embedding structure rather than using fixed traditional methods

Inventive Principle:
Principle #15Dynamics

4Device complexity

If traditional embedding techniques are used, then implementation is simpler, but path lengths increase

Engineering Contradiction:
Improveembedding complexityVSAvoidpath length
Core Design Contradiction:
Device complexityVSLength of moving object

Solution Approach 1:

The 3D lattice structure provides additional routing dimensions, allowing for shorter paths between nodes. By utilizing the z-dimension, the embedding can create more direct connections and reduce path lengths compared to constrained 2D planar embeddings

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8244662B2Graph embedding techniques
Publication Date: 2012.08.14 D WAVE SYSTEMS INC
  • US8244662B2 patent drawing
  • US8244662B2 patent drawing
  • US8244662B2 patent drawing

AI summary

Approaches to embedding source graphs into targets graphs in a computing system are disclosed. Such may be advantageously facilitate computation with computing systems that employ one or more analog processors, for example one or more quantum processors.