Graph Instruction Processing with Dynamic Input Readiness Detection
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Solution Overview
Problem
Conventional directed graphflow computing architectures face inefficiencies in processing graph instructions with three or more data inputs or output IDs, leading to increased pressure on data input reading, complex bypass logic, hardware implementation difficulties, and reduced performance due to expanded bit sizes or limited output ID scheduling.
Innovation Solution
The method involves detecting the readiness of input data for graph instructions, storing static data inputs in registers, and using pointer bitfields to efficiently process instructions with multiple inputs and outputs, reducing interference and improving reuse efficiency, while configuring output addresses in a regular format to avoid wasted instruction space and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an input port of an original graph instruction is reused for a corresponding composite graph instruction, then the data inputs can be transmitted to the operation unit, but the pressure of simultaneously reading the data inputs is increased and the difficulty of bypass logic is increased
Solution Approach 1:
The patent segments the input port resources by introducing separate input ports for composite graph instructions (third and fourth input ports) distinct from original graph instructions (first and second input ports). This segmentation allows composite instructions with multiple data inputs to be processed without increasing the reading pressure on shared input ports, thereby reducing bypass logic complexity while maintaining processing capability.
2Adaptability or versatility
If a quantity of bits occupied by an output ID is expanded, then graph instructions with multiple output IDs can be processed, but a majority of graph instructions with only one or two output IDs waste instruction space
Solution Approach 1:
The patent implements dynamic output ID allocation where the number of output IDs is not fixed but adapts to the specific instruction requirements. The graph instruction processing unit can dynamically allocate one, two, three, or more output IDs based on what each instruction actually needs, preventing the instruction space waste that occurs when all instructions are forced to use a uniform expanded format.
3Adaptability or versatility
If a CISC encoding manner is used to add output IDs to graph instruction format, then the encoding width can be adjusted, but the decoding difficulty of hardware is increased and large power consumption is generated
Solution Approach 1:
The patent applies local quality by making the instruction format adaptable to local needs of each specific graph instruction. Rather than using a uniform CISC encoding approach that increases hardware decoding complexity and power consumption, the system allows each instruction to have its output IDs configured according to its specific requirements, reducing the overall decoding burden and power consumption while maintaining flexibility.
4Loss of substance
If an output ID is limited and multiple output IDs share a same high-order bit, then the encoding can be compact, but the location of the output ID is limited and scheduling capability is greatly reduced
Solution Approach 1:
The patent resolves the contradiction by adding another dimension to the output ID space. Instead of limiting output IDs to share high-order bits (which restricts scheduling), the system expands the addressable output ID space to support up to 16 distinct output IDs per instruction. This dimensional expansion allows both compact encoding and full scheduling capability by providing sufficient address space without requiring bit-sharing limitations.
Data Source
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AI summary
This application provides a graph instruction processing method and apparatus, and relates to the field of computer technologies, to improve performance of a directed graphflow computing architecture. The method is applied to a processor, and includes: detecting whether a first input and a second input of a first graph instruction are in a ready-to-complete state, where the first input and/or the second input are or is a dynamic data input or dynamic data inputs of the first graph instruction (S301); obtaining static data input information of the first graph instruction from a first register when the first input and the second input are both in the ready-to-complete state, where the static data input information is used to indicate at least one input (S302), and each of the at least one input is a constant input or a temporary constant input; and processing the first graph instruction based on the first input, the second input, and the at least one input, to obtain a first processing result (S303).