Graph Model for Pipelined Processor Functional Coverage
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Solution Overview
Problem
Current microprocessor validation methods, particularly for deeply pipelined processor architectures, face challenges in ensuring comprehensive functional coverage due to the lack of a direct relationship between existing coverage measures and the actual functionality of the device, leading to inadequate testing of hazards, stalls, and exceptions.
Innovation Solution
A graph-theoretic model is developed to capture the structure and behavior of pipelined processors, enabling the definition of a functional fault model and automated test program generation that focuses on functional coverage, reducing the number of test sequences required to achieve a given fault coverage by several orders of magnitude.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional random and directed test cases are used for validation, then functional coverage can be attempted, but the number of test sequences required is excessively large and test generation time is long
Solution Approach 1:
The patent introduces an intermediate representation (IR) that serves as a mediator between the processor architecture and the test generation process. This IR captures the essential functional behavior of the processor in a simplified form, enabling efficient analysis and test case synthesis without requiring exhaustive simulation of the complete processor implementation, thus dramatically reducing test generation time while maintaining functional coverage.
Solution Approach 2:
The patent creates a simplified copy or model of the processor's functional behavior through the intermediate representation. This copy retains the critical functional characteristics needed for validation but omits implementation-specific details, allowing test cases to be generated efficiently from the model rather than from the full processor implementation, thereby reducing the computational burden and time required.
2Reliability
If complete processor modeling is performed to ensure comprehensive functional coverage, then all functional aspects can be tested, but the model size exceeds tool capacity restrictions
Solution Approach 1:
The patent extracts only the essential functional characteristics of the processor into the intermediate representation, separating the critical validation-relevant features from the complete processor implementation details. This extraction process creates a reduced model that fits within tool capacity limits while retaining sufficient fidelity to generate comprehensive functional test cases for hazards, stalls, and exceptions.
Solution Approach 2:
The patent segments the processor validation problem into two parts: a simplified intermediate representation for test generation and the complete processor implementation for final verification. This segmentation allows the complex complete model to be avoided during the computationally intensive test generation phase, while still enabling comprehensive functional coverage through the structured IR that captures essential behaviors.
3Productivity
If existing coverage measures like code coverage and toggle coverage are used, then validation can be performed, but these measures do not directly relate to the actual functionality of the device
Solution Approach 1:
The patent fundamentally changes the parameter used for measuring validation progress from traditional metrics like code coverage and toggle coverage to a new metric based on the intermediate representation. This new parameter directly reflects functional coverage by tracking which functional behaviors and interactions have been exercised, providing a precise measurement that directly relates to the actual functionality of the processor rather than surrogate metrics.
Data Source
AI summary
A functional coverage based test generation technique for pipelined architectures is presented. A general graph-theoretic model is developed that can capture the structure and behavior (instruction-set) of a wide variety of pipelined processors. A functional fault model is developed and used to define the functional coverage for pipelined architectures. Test generation procedures are developed that accept the graph model of the architecture as input and generate test programs to detect all the faults in the functional fault model. A graph model of the pipelined processor is automatically generated from the specification using functional abstraction. Functional test programs are generated based on the coverage of the pipeline behavior. Module level property checking is used to reduce test generation time.