Graph Neural Network for Digital Circuit Test Generation
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Solution Overview
Problem
Existing systems for digital circuit design verification require extensive hand-designed tests, which are time-consuming and costly, and lack efficiency in generating predictions about test outcomes.
Innovation Solution
A neural network system that processes digital circuit designs to generate machine-learned representations, allowing for automatic test generation and rapid prediction of test outcomes using self-attention based neural networks, graph neural networks, and prediction neural networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hand-designed tests are used for digital circuit verification, then test accuracy and reliability are improved, but time consumption and computational costs increase significantly
Solution Approach 1:
The patent uses neural networks to generate synthetic test cases that replicate the functionality of hand-designed tests. The neural network learns from existing test patterns and generates new test cases that cover similar functional areas, providing reliable verification without requiring manual creation of each test case.
Solution Approach 2:
The patent replaces the manual mechanical process of designing test cases by experts with an automated neural network system. The neural network processes circuit designs and automatically generates appropriate test cases, eliminating the time-consuming manual verification process while maintaining test quality through learned patterns from training data.
2Reliability
If hand-designed tests are created for each digital circuit design, then verification reliability is improved, but the quantity of engineer-hours required increases
Solution Approach 1:
The neural network system performs self-service by automatically generating test cases without human intervention. Once trained on existing test patterns, the system independently analyzes new circuit designs and generates appropriate test cases, freeing engineers from repetitive manual testing work and allowing them to focus on higher-value activities.
Solution Approach 2:
The patent transforms the verification process from a manual parameter-driven approach to an automated neural network approach. The system changes the fundamental parameters of test generation by using learned representations and neural network predictions instead of manual expert knowledge, significantly reducing the quantity of engineer-hours required while maintaining verification reliability.
3Measurement precision
If traditional test execution is performed, then accurate verification results are obtained, but computational costs and execution time increase
Solution Approach 1:
The patent performs preliminary action by using neural networks to predict test outcomes before actual execution. The trained neural network can quickly assess the likelihood of test failures or successes based on circuit characteristics, allowing verification to be performed more efficiently by focusing computational resources only on critical test cases that need detailed analysis.
Data Source
AI summary
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating learned representations of digital circuit designs. One of the systems includes obtaining data representing a program that implements a digital circuit design, the program comprising a plurality of statements; processing the obtained data to generate data representing a graph representing the digital circuit design, the graph comprising: a plurality of nodes representing respective statements of the program, a plurality of first edges each representing a control flow between a pair of statements of the program, and a plurality of second edges each representing a data flow between a pair of statements of the program; and generating a learned representation of the digital circuit design, comprising processing the data representing the graph using a graph neural network to generate a respective learned representation of each statement represented by a node of the graph.