Graph Neural Network Partitioning for Multi-Processor Feature Aggregation

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Solution Overview

Problem

Conventional methods for processing graph-structured data using a single processor are inefficient, leading to prolonged processing times, increased latency, and potential system failures due to the massive size and complexity of the data, especially in applications like molecular dynamics.

Innovation Solution

The method involves segmenting the input graph into multiple partial input graphs and utilizing a plurality of processors to generate network features in parallel, optimizing computational resources through a graph neural network (GNN) to reduce processing time and enhance efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single processor is used to process graph-structured data, then device complexity is reduced, but processing time increases and productivity decreases

Engineering Contradiction:
Improveprocessing speedVSAvoidprocessor configuration
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The input graph is divided into multiple partial input graphs and assigned to different processors for parallel processing. Each processor handles a subset of the graph data independently, then results are aggregated to produce the final output. This segmentation enables simultaneous computation across multiple processors, dramatically improving processing speed for large-scale graph data while maintaining manageable device complexity through modular architecture.

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple processors are used to process graph data in parallel, then productivity increases, but communication overhead and system complexity increase

Engineering Contradiction:
Improvecomputational efficiencyVSAvoidprocessor coordination
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The graph data is segmented into partial graphs that can be processed independently by different processors, minimizing the need for frequent inter-processor communication during the computation phase. Each processor works autonomously on its assigned segment, reducing communication overhead.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A coordinator component manages the distribution of partial graphs to processors and aggregates the results. This intermediary handles the complexity of processor coordination, result collection, and final computation aggregation, isolating the parallel processing complexity from the individual processors and simplifying their operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of time

If the entire input graph is processed at once, then measurement precision is maintained, but processing time becomes unacceptably long

Engineering Contradiction:
Improveprocessing timeVSAvoidcomputation accuracy
Core Design Contradiction:
Loss of timeVSMeasurement precision

Solution Approach 1:

The input graph is divided into multiple partial input graphs that are processed in parallel by different processors. Each processor computes features for its assigned segment with the same precision as whole-graph processing would provide, but the overall processing time is reduced through simultaneous execution. The segmentation maintains computational accuracy while enabling time-efficient parallel processing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The results from multiple partial graph computations are merged and aggregated to produce the final output. This combining step ensures that the precision and accuracy characteristics of the original whole-graph computation are preserved, while benefiting from the time savings of parallel processing. The aggregation systematically integrates results from all processor segments.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250232172A1Method and apparatus for employing graph neural network by using plurality of processors
Publication Date: 2025.07.17 SAMSUNG ELECTRONICS CO LTD
  • US20250232172A1 patent drawing
  • US20250232172A1 patent drawing
  • US20250232172A1 patent drawing

AI summary

A method including obtaining an input graph including a plurality of network components, where each of the plurality of network components include a plurality of nodes and a plurality of edges, segmenting the input graph into a plurality of partial input graphs, where the plurality of partial input graphs includes a first partial input graph and a second partial input graph, generating network features based on the plurality of partial input graphs, where each of the network features includes a connectivity relation between a network component and an adjacent network component among the plurality of network components in the input graph, transmitting a network feature from the first partial input graph to an adjacent network feature in the second partial input graph to obtain an aggregated network feature, and updating the network features of the plurality of network components based on the aggregated network feature.