High-Speed Graph Processor with Segmented Memory Channels
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Solution Overview
Problem
The processing of large, sparse graphs is hindered by delays in transferring data between memory and processor, exacerbated by the large size and sparseness of graphs, leading to inefficient memory access patterns and cache usage.
Innovation Solution
A specialized processor architecture that closely couples a high-bandwidth, small access granularity memory with dedicated parallel processing circuits, allowing independent memory channels for parallel operations and reducing memory bottlenecks through the use of multiple processing circuits associated with multiple memory channels, enabling efficient search operations on sparse graphs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard computer architectures are used for graph processing, then general-purpose computing is maintained, but processing speed is limited by memory transfer delays
Solution Approach 1:
The system segments the graph processing workload across multiple independent processing circuits (32, 34) that operate in parallel on different memory channels. Each processing circuit handles a portion of the frontier vertices independently, allowing simultaneous neighbor identification and new frontier determination without sequential bottlenecks.
Solution Approach 2:
The patent introduces an intermediary high-bandwidth memory structure (12) with multiple independent channels that acts as a buffer between the processing circuits and the data storage. This memory intermediary enables parallel access patterns and reduces the impact of random memory access by providing dedicated channels for different processing circuits.
2Quantity of substance
If graphs are stored in standard memory with random access patterns, then data storage is achieved, but memory cache effectiveness is reduced due to sparseness
Solution Approach 1:
The patent transitions from two-dimensional planar memory organization to a three-dimensional memory cube architecture. This dimensional change allows for higher density storage while providing multiple access paths and channels, enabling parallel processing circuits to access different portions of the graph data simultaneously without cache conflicts.
3Productivity
If multiple processing circuits access memory independently, then parallel processing is achieved, but memory access conflicts may occur
Solution Approach 1:
The memory system is segmented into multiple independent channels (15) that are exclusively assigned to specific processing circuits. This channel segmentation eliminates access conflicts by ensuring that each processing circuit has dedicated memory bandwidth, allowing full parallel processing capability without interference between circuits.
Data Source
AI summary
A computer architecture for graph processing employs a high-bandwidth memory closely coupled to independent processing elements for searching through a graph using a first set of processing elements operating simultaneously to determine neighbors to a current frontier and second processing elements operating simultaneously to determine a next frontier, this process being repeated to search through graph nodes.