Fine-Grained Graph Processor Scheduler Using Dynamic Scoreboard
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Solution Overview
Problem
Current scheduling systems in microprocessor-based systems are inflexible and lack re-programmability due to static scheduling, which restricts the ability to dynamically adjust instruction execution paths and resource allocation, leading to inefficiencies in multi-core processors and graph processors.
Innovation Solution
A general-purpose scheduler is developed for fine-grained graph processors that allows dynamic scheduling and resource allocation across multiple execution units, optimizing execution paths and resource utilization by using a scoreboard structure to check availability and prioritize instructions based on resource constraints, timing, and path constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If static scheduling is used in microprocessor-based systems, then implementation simplicity is maintained, but flexibility and re-programmability deteriorate
Solution Approach 1:
The patent implements dynamic scheduling by making the scheduler capable of real-time decision-making based on current system state. The scheduler uses a scoreboard structure to track resource availability and instruction status, dynamically selecting which instructions to execute next rather than following a predetermined static schedule. This allows the system to adapt to changing conditions while maintaining manageable complexity through structured resource tracking.
2Adaptability or versatility
If dynamic scheduling is implemented, then flexibility and resource utilization improve, but system complexity increases
Solution Approach 1:
The scoreboard structure serves as an intermediary data structure that simplifies dynamic scheduling by centralizing resource availability and instruction status information. Rather than complex interconnections between multiple scheduling components, the scoreboard provides a unified interface for tracking and decision-making, reducing overall system complexity while enabling flexible dynamic scheduling.
3Ease of manufacture
If static instruction ordering is used, then compilation simplicity is maintained, but execution efficiency deteriorates
Solution Approach 1:
The system separates compilation simplicity from execution efficiency by using static code generation for compilation ease, then implementing dynamic scheduling at runtime to optimize execution. The scoreboard-enabled scheduler reorders and selects instructions dynamically based on resource availability and data dependencies, achieving high execution efficiency without complicating the compilation process.
4Loss of time
If resource binding is performed statically, then compilation time is reduced, but resource utilization efficiency deteriorates
Solution Approach 1:
The system performs minimal static resource binding during compilation to keep compilation time short, then uses dynamic scheduling at runtime to optimize resource allocation. The scoreboard tracks actual resource availability and instruction readiness, allowing the system to bind instructions to resources dynamically based on real-time conditions, thereby maximizing resource utilization without extending compilation time.
Data Source
AI summary
A novel scheduler design is provided that schedules a set of operations to an array of similar or dissimilar, candidate operations on a cycle by cycle basis, out of a total number of operations. The array of similar or dissimilar units can be atomic in nature or ALU like or complete processors. The scheduler is able to map the operations in a data flow/sequencing graph to the two dimensional or 3 dimensional array (which can be extended to a multi-dimensional array) optimally so as to minimize the total execution times. The mapping is path based computation, where a particular sequence of instructions is routed through the underlying matrix in path that minimized the number of memory hops.