Graph Streaming Scheduler Segments Code Blocks

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Solution Overview

Problem

Current graph stream processing systems face challenges in efficiently managing code execution across multiple processors due to data dependencies, which limits throughput in computation-rich applications.

Innovation Solution

A scheduler system that segments program code into code blocks, schedules threads based on resource availability, and uses command buffers to manage data dependencies, enabling parallel execution across multiple processors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If code is executed in parallel across multiple processors, then throughput is improved, but data dependencies cause scheduling complexity and reduce parallel processing efficiency

Engineering Contradiction:
ImprovethroughputVSAvoidscheduling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments code into discrete code blocks that can be independently scheduled and executed. Each code block represents a unit of work that can be assigned to different processors, enabling parallel execution while maintaining manageability through modular segmentation of the computation graph.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary analysis of data dependencies between code blocks before execution. By pre-computing the execution order and identifying independent code blocks that can run in parallel, the scheduler prepares the execution plan in advance, reducing runtime complexity and enabling efficient parallel processing.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If data dependencies are strictly managed to ensure correctness, then reliability is improved, but parallel processing efficiency decreases

Engineering Contradiction:
Improvedata dependency managementVSAvoidparallel processing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The scheduler dynamically adjusts execution based on data dependency requirements. It identifies code blocks with no dependencies and executes them immediately in parallel, while temporarily suspending or reordering blocks that require data from other blocks. This dynamic scheduling maintains reliability by respecting dependency constraints while maximizing parallel execution of independent tasks.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent introduces an intermediary scheduling layer that mediates between data producers and consumers. This scheduler acts as a buffer, managing data flow and synchronization between code blocks, ensuring that consumer blocks receive data from producer blocks before execution, thereby maintaining reliability while enabling parallel processing where possible.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If more processors are utilized to increase throughput, then productivity is improved, but managing multiple processors and data dependencies becomes more challenging

Engineering Contradiction:
ImprovethroughputVSAvoidprocessor management
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The system implements self-service mechanisms where code blocks contain embedded metadata about their data dependencies and resource requirements. The scheduler automatically reads this metadata and makes scheduling decisions without manual intervention, enabling the system to self-manage multiple processors and data dependencies through automated analysis and assignment of code blocks to appropriate processing units.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11416282B2Configurable scheduler in a graph streaming processing system
Publication Date: 2022.08.16 BLAIZE INC
  • US11416282B2 patent drawing
  • US11416282B2 patent drawing
  • US11416282B2 patent drawing

AI summary

Systems, apparatuses and methods are disclosed for scheduling threads comprising of code blocks in a graph streaming processor (GSP) system. One system includes a scheduler for scheduling plurality of threads, the plurality of threads includes a set of instructions operating on the graph streaming processors of GSP system. The scheduler comprises a plurality of stages where each stage is coupled to an input command buffer and an output command buffer. A portion of the scheduler is implemented in hardware and comprises of a command parser operative to interpret commands within a corresponding input command buffer, a thread generator coupled to the command parser operate to generate the plurality of threads, and a thread scheduler coupled to the thread generator for dispatching the plurality of threads for operating on the plurality of graph streaming processors.