Graph-Based Tamper Verification for Embedded Storage

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Solution Overview

Problem

Conventional technologies face difficulties in verifying the presence or absence of tampering in embedded equipment software from outside the equipment, particularly in proving that no unauthorized software is added to the free area.

Innovation Solution

A verification device that generates a graph based on the free storage area of the target equipment, calculates hash values for software blocks, and verifies tampering by comparing responses to challenges, using Localized Stacked Expanders and hash trees to ensure the integrity of the software area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If whitelist-type detection technology is used to verify software integrity, then verification of software area can be achieved, but verification of free area tampering is difficult

Engineering Contradiction:

Improvesoftware integrity verificationVSAvoidfree area tampering detection

Core Design Contradiction:

ReliabilityVSMeasurement precision

Solution Approach 1:

The storage is segmented into software area and free area, with separate verification mechanisms. The software area is verified using whitelist-type hash verification, while the free area is verified using graph-based challenge-response mechanisms, allowing targeted verification of each region's integrity

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A graph structure serves as an intermediary between the verification device and the storage areas. The graph nodes represent挑战和响应 relationships that indirectly verify both software area and free area integrity without directly accessing or exposing the storage contents

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If external verification of embedded equipment is implemented, then security verification is improved, but system complexity increases

Engineering Contradiction:

Improveexternal verification capabilityVSAvoidverification system structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The verification device is designed as a universal system that can verify multiple types of embedded equipment through standardized graph-based challenge-response protocols. The same verification framework handles both software area and free area verification, reducing overall system complexity despite the comprehensive verification capability

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

Instead of verifying the actual software and free area contents directly, the system uses hash values and graph structures as copies or representations of the storage state. This allows external verification without requiring direct access to or replication of the actual storage contents, simplifying the verification process

Inventive Principle:

Principle #26Copying

Data Source

PatentUS12067152B2Verification device, verification system, verification method, and verification program

Publication Date: 2024.08.20 NIPPON TELEGRAPH & TELEPHONE CORP

AI summary

A storage unit stores a size of a free area of storage of target equipment, and software saved in the storage. The generation unit generates a graph including a number of nodes according to the size of the free area of the storage, and transmits the graph to the target equipment. The calculation unit calculates a hash value corresponding to each software block saved in the storage. The verification unit verifies the presence or absence of tampering of the storage of the target equipment using the hash value corresponding to the block calculated, a response calculated using the graph returned to a challenge that specifies a node of the graph, and a hash value corresponding to the block returned as the response to the challenge that specifies the block.