Graph Traversal Architecture Using Degree-Ordered Memory Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Graph-traversal operations in scale-free graphs are inefficient due to redundant edge checks and irregular memory access, especially in large graphs like those used by social networking sites, which slow down processing.
Innovation Solution
A computer architecture that sequences vertex data by degree during bottom-up traversal, optimizes memory access by loading frequently accessed high-index vertex data in fast memory, and uses compression to reduce storage footprint, employing a hybrid traversal strategy with top-down and bottom-up modes and parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional graph-traversal is used on scale-free graphs, then the traversal covers all vertices, but redundant edge checks and irregular memory access slow down processing speed
Solution Approach 1:
The patent applies preliminary action by pre-sorting vertices according to their degree (number of connections) before traversal begins. This pre-arrangement allows the traversal algorithm to systematically process high-degree vertices first, minimizing redundant edge checks and improving overall traversal speed without requiring changes to the core traversal logic during execution.
Solution Approach 2:
The patent changes the parameter of vertex processing order from conventional approaches to degree-based ordering. By sorting vertices according to their degree parameter and processing them in descending order, the algorithm efficiently handles scale-free graphs where a small number of high-degree vertices connect to many low-degree vertices, reducing redundant checks significantly.
2Speed
If graph data is stored in memory, then traversal can proceed, but large graph sizes exceed fast memory capacity, requiring slower memory access
Solution Approach 1:
The patent applies segmentation by dividing the large graph data into multiple partitions or blocks that can be selectively loaded into fast memory. Instead of loading the entire graph, the system segments the data and loads only the necessary portions (e.g., vertices and edges relevant to the current traversal phase) into fast memory, reducing memory pressure and improving access speed.
Solution Approach 2:
The patent introduces a new dimension to memory management by implementing a hierarchical memory architecture that combines fast memory (for active traversal data) and slow memory (for persistent graph storage). This dimensional approach allows the system to maintain large graphs in slow memory while efficiently accessing frequently used portions in fast memory, effectively bridging the capacity-speed gap.
3Productivity
If hybrid top-down and bottom-up traversal is used, then traversal efficiency improves, but atomic updating requirements for top-down mode increase system complexity
Solution Approach 1:
The patent applies dynamics by making the traversal mode flexible and adaptive rather than fixed. The system can dynamically switch between top-down and bottom-up traversal modes depending on the graph structure and traversal progress. This dynamic approach allows the algorithm to exploit the strengths of each mode (top-down for systematic coverage, bottom-up for efficiency in scale-free graphs) while avoiding the weaknesses (atomic updating complexity) of any single mode.
Solution Approach 2:
The patent applies inversion by reversing the conventional top-down approach in certain phases by implementing bottom-up traversal. Instead of starting from root vertices and moving downward, the bottom-up mode starts from leaf vertices and moves upward, which naturally avoids the atomic updating problems of top-down approaches in scale-free graphs while maintaining traversal completeness.
Data Source
AI summary
A computer architecture for graph-traversal provides a processor for bottom-up sequencing through the graph data according to vertex degree. This ordered sequencing reduces redundant edge checks. In one embodiment, vertex adjacency data describing the graph may be allocated among different memory structures in the memory hierarchy to provide faster access to vertex data associated with vertices of higher degree reducing data access time. The adjacency data also may be coded to provide higher compression in memory of vertex data having high vertex degree.