Graphene 2D Semiconductor Memory Device Scalable Manufacturing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices incorporating 2D materials, such as graphene, face manufacturing complexities and are not easily scalable due to their intricate structures, making it challenging to produce high-performance, high-density memory devices with large-area applications.
Innovation Solution
A memory device design featuring a simple stacked structure with a graphene layer and a 2D semiconductor layer, utilizing hexagonal boron nitride as insulation, and a capacitor configuration that allows for easy manufacturing and scalability, enabling high-density memory arrays with flexible and transparent characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a transfer process of 2D material such as graphene is used in existing memory devices, then the device can incorporate 2D materials for high performance, but the manufacturing process becomes complicated and difficult to scale to large-area applications
Solution Approach 1:
The patent extracts and eliminates the transfer process from the manufacturing workflow by directly growing graphene and 2D semiconductor layers on the substrate using CVD and other deposition techniques. This removes the complex transfer step while retaining the high-performance benefits of 2D materials in the memory device structure.
Solution Approach 2:
The patent employs universal deposition techniques such as chemical vapor deposition (CVD) that can simultaneously grow multiple 2D material layers (graphene, h-BN, 2D semiconductors) on the same substrate. This multi-functional approach simplifies the manufacturing process by consolidating multiple steps into a single integrated growth process suitable for large-area production.
2Reliability
If existing memory device structures are used with 2D materials, then the device can achieve high performance, but the structure becomes relatively complicated making it difficult to manufacture
Solution Approach 1:
The patent segments the memory device into distinct functional layers with clear interfaces: bottom electrode, gate dielectric, graphene layer, 2D semiconductor layer, and top electrode. This segmentation creates a simple stacked structure where each layer performs a specific function, reducing overall structural complexity while maintaining high device performance through optimized layer-by-layer architecture.
3Reliability
If existing memory device structures are used with 2D materials, then the device can achieve high performance, but it is difficult to apply the device to large-area (large-scale) processes
Solution Approach 1:
The patent transitions from conventional planar processing to vertical stacked architecture, where multiple functional layers are stacked in the vertical dimension. This dimensional change enables large-area scalability because the vertical stacking approach is compatible with wafer-scale deposition techniques, allowing simultaneous fabrication across large substrate areas while maintaining high device performance through the 2D material layers.
Data Source
AI summary
Disclosed are memory devices including a two-dimensional (2D) material, methods of manufacturing the same, and methods of operating the same. A memory device may include a transistor, which includes graphene and 2D semiconductor contacting the graphene, and a capacitor connected to the transistor. The memory device may include a first electrode, a first insulation layer, a second electrode, a semiconductor layer, a third electrode, a second insulation layer, and a fourth electrode which are sequentially arranged. The second electrode may include the graphene, and the semiconductor layer may include the 2D semiconductor. Alternatively, the memory device may include first and second electrode elements, a graphene layer between the first and second electrode elements, a 2D semiconductor layer between the graphene layer and the first electrode element, and a dielectric layer between the graphene layer and the second electrode.