Graphene Barrier Layer for Semiconductor Interconnects
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Solution Overview
Problem
As semiconductor devices shrink in size, copper oxidation and diffusion issues arise between copper and common insulating dielectric materials, leading to corrosion, delamination, and device failure, which existing barrier layers like titanium nitride and tantalum nitride struggle to address effectively at smaller scales.
Innovation Solution
The use of a graphene-based barrier layer formed using a self-assembly monolayer (SAM) on select surfaces within semiconductor interconnect structures, which prevents copper oxidation and diffusion by maximizing conductive material volume and providing chemical stability through annealing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper is used as conductive material in interconnect structures, then electrical conductivity is improved, but copper oxidation and diffusion occur leading to device failure
Solution Approach 1:
A graphene barrier layer is introduced as an intermediary between copper and dielectric materials. This single-atom-thick graphene layer prevents copper oxidation and diffusion while maintaining electrical conductivity, solving the harmful interaction between copper and surrounding materials.
Solution Approach 2:
The patent uses an ultra-thin graphene film (single-atom thickness) as a protective barrier. This thin film approach provides effective protection against copper oxidation and diffusion without adding significant thickness, enabling continued miniaturization of interconnect structures.
2Reliability
If traditional barrier layers like titanium nitride or tantalum nitride are used, then copper diffusion is prevented, but sheet resistance increases and device scaling becomes difficult
Solution Approach 1:
The patent replaces traditional thick barrier layers with an ultra-thin graphene film. This thin film provides equivalent or superior barrier effectiveness against copper diffusion while maintaining low sheet resistance, enabling precise control of electrical properties in scaled devices.
Solution Approach 2:
The invention changes the fundamental parameter of barrier layer thickness from nanometer-scale (traditional materials) to atomic-scale (graphene). This parameter change achieves both effective copper diffusion prevention and low sheet resistance, resolving the contradiction between barrier effectiveness and electrical performance.
3Productivity
If device geometry is reduced to enable miniaturization, then production efficiency increases, but copper oxidation and diffusion become more severe
Solution Approach 1:
The ultra-thin graphene film provides effective copper protection even in highly scaled geometries where traditional barriers would occupy excessive space. This enables continued device miniaturization while maintaining copper stability and preventing oxidation and diffusion.
Solution Approach 2:
The patent creates a composite structure combining copper conductors with graphene barrier layers. This composite approach leverages the high conductivity of copper and the protective properties of graphene, enabling reliable operation in miniaturized interconnect structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves low sheet resistance, low contact resistance, enhanced device reliability, and controllable thickness, enabling further miniaturization of semiconductor devices without performance sacrifice, particularly for aggressive design rules below 7 nm or 5 nm.
Implementation Method 1
graphene-based barrier layer formed using a self-assembly monolayer (SAM) on select surfaces within semiconductor interconnect structures
Implementation Method 2
self-assembly monolayer (SAM) on select surfaces
Data Source
AI summary
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer on select surfaces using a self-assembly monolayer (SAM). The SAM layer can be selectively formed on dielectric surfaces and annealed to form thin graphene barrier layers. The thickness of the graphene barrier layers can be selected by choosing different alkyl groups of the SAM layer.