Graphene Base Transistor Fabrication with Dielectric Fill
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Solution Overview
Problem
The integration of graphene base transistors into standard semiconductor fabrication processes is challenging due to the sensitivity of graphene layers, which are prone to damage during processing steps, and the difficulty in limiting graphene deposition to the desired lateral extension without damaging the layer.
Innovation Solution
A graphene base transistor design featuring a dielectric filling layer with a flush upper surface, a conductive base-contact structure, and a collector stack that protects the graphene layer during processing, allowing for integration into existing semiconductor processes without additional processing steps that could damage the graphene layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If graphene base transistors are integrated into standard semiconductor fabrication processes, then productivity and manufacturing scalability are improved, but the graphene layer is damaged during processing steps
Solution Approach 1:
The emitter and collector structures are fabricated in advance, creating a pre-assembled stack that defines the precise lateral boundaries where graphene will be deposited. This preliminary structuring ensures that subsequent graphene deposition is automatically limited to the correct region, eliminating the need for additional processing steps that could damage the graphene layer while maintaining compatibility with standard semiconductor fabrication processes
Solution Approach 2:
The patent introduces an intermediary approach where the emitter and collector structures serve as boundary-defining elements that mediate between the deposition process and the final graphene base structure. These structures act as physical guides that protect the graphene layer during fabrication by pre-establishing the spatial constraints, allowing standard fabrication processes to be used without directly exposing the graphene to damaging processing steps
2Manufacturing precision
If additional processing steps are added to limit graphene deposition to desired lateral extension, then manufacturing precision is improved, but device complexity and process difficulty increase
Solution Approach 1:
The emitter and collector structures are fabricated beforehand to establish the lateral boundaries. This preliminary action creates a self-guiding structure that automatically limits graphene deposition to the desired region without requiring additional masking or patterning steps, thereby achieving high manufacturing precision while avoiding increased process complexity
Solution Approach 2:
The patent merges the boundary-defining function with the existing emitter and collector structures. Instead of adding separate components to control lateral extension, the design combines the structural elements that must exist for device operation with the elements that define deposition boundaries, eliminating additional processing steps while maintaining precise lateral control
Data Source
AI summary
A graphene base transistor comprises on a semiconductor substrate surface an emitter pillar and an emitter-contact pillar, which extend from a pillar foundation in a vertical direction. A dielectric filling layer laterally embeds the emitter pillar and the emitter-contact pillar above the pillar foundation. The dielectric filling layer has an upper surface that is flush with a top surface of the emitter pillar and with the at least one base-contact arm of a base-contact structure. A graphene base forms a contiguous layer between a top surface of the emitter pillar and a top surface of the base-contact arm. A collector stack and the base have the same lateral extension parallel to the substrate surface and perpendicular to those edges of the top surface of the emitter pillar and the base-contact arm that face each other.