Graphene Buried Conductive Layer Void Prevention
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly due to issues such as void formation during fabrication.
Innovation Solution
A semiconductor device design incorporating a buried conductive layer made of graphene, with buried covering layers and a capping layer, which increases the cross-sectional area of the conductive layer and prevents void formation, enhancing conductivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimensions of semiconductor devices are scaled down, then computing ability is improved, but void formation occurs during fabrication and reliability deteriorates
Solution Approach 1:
The patent employs a composite structure consisting of a buried conductive layer (graphene), buried dielectric layer, buried covering layers, and buried capping layer. This multi-layer composite design prevents void formation while maintaining scaled dimensions, thereby improving reliability without sacrificing computing ability.
Solution Approach 2:
The patent implements a nested layer structure where the buried conductive layer is positioned within the first substrate, surrounded by buried dielectric layer, which is in turn covered by buried covering layers and topped with a buried capping layer. This nested configuration ensures structural integrity and prevents void formation during fabrication scaling.
2Reliability
If the cross-sectional area of the conductive layer is increased, then conductivity is improved, but device complexity increases
Solution Approach 1:
The patent increases the cross-sectional area of the conductive layer by extending it vertically through the substrate thickness direction, rather than expanding it laterally. This dimensional approach enhances conductivity while maintaining a compact lateral footprint, thereby avoiding increased device complexity.
Solution Approach 2:
The patent uses graphene as the buried conductive layer material, which provides high conductivity with atomic thinness. This allows the conductive layer to achieve excellent electrical properties without adding significant structural complexity to the device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves the conductivity and performance of semiconductor devices by increasing the cross-sectional area of the graphene-based conductive layer and prevents void formation, thereby enhancing the reliability of the semiconductor device.
Implementation Method 1
a buried conductive layer including a lower portion positioned on the buried dielectric layer and an upper portion positioned on the lower portion... The buried conductive layer includes graphene
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first substrate, a buried dielectric layer inwardly positioned in the first substrate, a buried conductive layer including a lower portion positioned on the buried dielectric layer and an upper portion positioned on the lower portion, a buried capping layer positioned on the upper portion, and buried covering layers positioned between the buried capping layer and the buried dielectric layer and between the upper portion of the buried conductive layer and the buried dielectric layer. The buried conductive layer includes graphene.