Graphene Interconnects via Catalyst Protrusions for LSI Reliability
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Solution Overview
Problem
The miniaturization of LSI wiring structures leads to increased electric resistivity and reliability degradation due to interfacial inelastic scattering of electrons and stress migration or electro-migration, which existing metallic materials like copper fail to address effectively.
Innovation Solution
The use of graphene as a wiring material, where a catalyst layer with protruding areas is formed on a foundation layer with different materials, allowing graphene to grow and form continuous, high-quality layers with varying thicknesses for efficient interconnects, reducing resistance and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper is used as wiring material for LSI, then electrical conductivity is maintained at acceptable levels, but electric resistivity increases due to interfacial inelastic scattering of electrons in miniaturized structures
Solution Approach 1:
The patent changes the material parameter from conventional metals (copper) to graphene, which has fundamentally different electronic properties. Graphene's two-dimensional structure and unique band structure enable ballistic electron transport, eliminating interfacial inelastic scattering that plagues miniaturized copper interconnects. This parameter change in material composition directly addresses the increasing electric resistivity problem in scaled-down LSI wiring.
Solution Approach 2:
The patent employs a composite structure consisting of a catalyst layer (first layer) and a graphene layer (second layer). The catalyst layer serves as a substrate for graphene growth and provides structural support, while the graphene layer provides the low-resistance conduction path. This composite material approach allows utilization of graphene's superior electrical properties while maintaining structural integrity in miniaturized interconnect structures.
2Productivity
If wiring structure is miniaturized to advance LSI fabrication, then integration density increases, but reliability degrades due to stress migration and electro-migration
Solution Approach 1:
The patent changes the mechanical and electrical parameters of the wiring material by transitioning from copper to graphene. Graphene's exceptional mechanical strength and chemical stability provide inherent resistance to stress migration, while its high current carrying capacity and ballistic transport properties reduce electro-migration effects. This enables continued miniaturization and integration density improvement without the reliability penalties observed in conventional copper interconnects.
Solution Approach 2:
The catalyst layer is designed as a temporary structure that serves its purpose during graphene formation and can be removed or left as a supportive underlayer. This allows optimization of the graphene layer properties without being constrained by the need to preserve the catalyst material, enabling creation of robust, miniaturized interconnect structures with improved reliability.
3Object-affected harmful factors
If graphene is used as wiring material, then electric resistivity decreases due to quantized conductance, but manufacturing complexity increases requiring catalyst layer formation and controlled growth
Solution Approach 1:
The patent performs preliminary action by forming the catalyst layer before graphene growth. The catalyst layer is prepared with specific patterns and thicknesses to control subsequent graphene nucleation and growth. This preliminary structuring enables precise control over graphene formation, reducing manufacturing complexity despite the advanced material being used. The catalyst layer acts as a pre-configured template that guides graphene development into the desired interconnect structure.
Solution Approach 2:
The catalyst layer serves as an intermediary between the substrate and the final graphene interconnect structure. It mediates the graphene growth process by providing controlled nucleation sites and influencing grain structure development. This intermediary layer simplifies the overall manufacturing process by enabling bottom-up self-assembly of high-quality graphene, reducing the need for complex post-processing steps while achieving the desired low-resistance properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor devices with low resistance and improved reliability by utilizing graphene's quantized conductance, effectively mitigating the issues of increased electric resistivity and reliability degradation in LSI wiring.
Implementation Method 1
a catalyst layer with protruding areas is formed on a foundation layer with different materials, allowing graphene to grow
Data Source
AI summary
According to one embodiment, a semiconductor device is disclosed. The device includes a foundation layer including first and second layers being different from each other in material, and the foundation layer including a surface on which a boundary of the first and second layers is presented, a catalyst layer on the surface of the foundation layer, and the catalyst layer including a protruding area. The device further includes a graphene layer being in contact with the protruding area.