Graphene Channel Semiconductor Device for Silicon Scaling Limits
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Solution Overview
Problem
The miniaturization of silicon-based electronics is approaching its limits due to material properties, necessitating alternative technologies that can achieve smaller feature sizes and lower power consumption while allowing large-scale integration using lithographic patterning methods.
Innovation Solution
A semiconductor device with a graphene layer as the channel, including a substrate with a dielectric layer, a graphene layer overlying the dielectric layer, a back gate structure underlying the graphene layer, and a semiconductor-containing layer with source and drain regions separated by an upper gate structure, formed using specific doping and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If silicon-based microelectronics are miniaturized to reduce component size and power consumption, then smaller feature sizes and lower power consumption are achieved, but material property limitations at the nanoscale level prevent further miniaturization
Solution Approach 1:
The patent changes the fundamental material parameter from silicon to graphene, exploiting graphene's superior electrical conductivity, carrier mobility, and mechanical strength to overcome silicon's nanoscale limitations while enabling continued miniaturization
Solution Approach 2:
The device structure combines graphene channel layer with semiconductor-containing source and drain regions, creating a composite material system that leverages graphene's exceptional properties for the channel while maintaining compatibility with existing semiconductor fabrication processes
2Productivity
If component size is reduced to increase integration density, then large-scale integration is enabled, but silicon material properties impose fundamental limits on further reduction
Solution Approach 1:
By transitioning to graphene with its unique two-dimensional structure and superior electrical properties, the patent enables continued scaling to smaller dimensions while maintaining or improving integration density, overcoming silicon's physical limits
3Use of energy by moving object
If alternative technology is developed to sustain microelectronics beyond silicon limits, then smaller feature sizes and energy efficiency are achieved, but new material processing and integration methods are required
Solution Approach 1:
The patent segments the device into distinct functional regions: graphene channel layer for high-speed electron transport, semiconductor-containing source and drain regions for charge injection, and gate structures for control, allowing each component to be optimized independently while maintaining overall device performance
Solution Approach 2:
The graphene layer serves multiple functions simultaneously: it acts as the channel for carrier transport, provides mechanical support for the device structure, and enables continued scaling due to its two-dimensional nature, reducing the need for additional specialized components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the development of smaller, more energy-efficient electronic components beyond the limitations of silicon-based microelectronics, facilitating large-scale integration and maintaining the efficiency of lithographic patterning methods.
Implementation Method 1
diffusing the first conductivity type dopant from the dielectric layer comprising the first conductivity type dopant into the semiconductor-containing layer to provide a source region and a drain region
Implementation Method 2
implanting a gate dopant of a second conductivity type, opposite that of the first conductivity type, into the exposed portion of the semiconductor-containing layer to provide an upper gate structure and into the substrate underlying the upper gate structure to provide a back gate structure
Data Source
AI summary
The present invention, in one embodiment, provides a semiconductor device including a substrate having an dielectric layer; at least one graphene layer overlying the dielectric layer; a back gate structure underlying the at least one graphene layer; and a semiconductor-containing layer present on the at least one graphene layer, the semiconductor-containing layer including a source region and a drain region separated by an upper gate structure, wherein the upper gate structure is positioned overlying the back gate structure.