Graphene-Channel Devices Bonded to CMOS Wafers
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Solution Overview
Problem
Current graphene-based devices face challenges in integrating with CMOS technology due to temperature incompatibilities and issues with parasitic capacitance and residual series resistance, which hinder their performance in high-frequency applications.
Innovation Solution
A novel 3D integration approach is employed, where graphene and CMOS circuitry are separately fabricated and then bonded using an oxide-to-oxide bond, allowing for non-overlapping gate contacts and self-aligned doping to minimize parasitic capacitance and residual series resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If graphene is grown epitaxially from silicon carbide substrates, then high carrier mobility is achieved, but the reaction temperature of at least 1,200°C greatly exceeds the temperature cap of 350°C to 400°C for CMOS processes
Solution Approach 1:
The device is divided into two separate wafers: a first wafer containing the graphene channel formed at high temperature, and a second wafer containing the CMOS device layer formed at low temperature. These wafers are subsequently bonded together, allowing each component to be fabricated under its optimal temperature conditions without interfering with the other.
Solution Approach 2:
The solution transitions from a planar integration approach to a three-dimensional stacked architecture. By bonding the graphene wafer and CMOS wafer together through their oxide layers, the patent creates a vertical integration structure that resolves the temperature incompatibility issue.
2Reliability
If the gate contact overlaps with the source/drain metal contacts, then good gate control is ensured, but significant parasitic capacitance is introduced
Solution Approach 1:
The patent utilizes the third dimension (vertical stacking) to separate the gate contact from the source/drain contacts. The gate contact is formed on the CMOS wafer while the source/drain contacts are on the graphene wafer, allowing them to be vertically aligned without lateral overlap, thus eliminating parasitic capacitance while maintaining gate control through the oxide layer.
3Adaptability or versatility
If graphene and CMOS circuitry are integrated using conventional methods, then device functionality is achieved, but temperature incompatibilities and process limitations prevent successful integration
Solution Approach 1:
The patent separates the graphene and CMOS fabrication processes into distinct stages on separate wafers. The graphene wafer is fabricated first at high temperature, then a CMOS wafer is fabricated separately at low temperature, and finally the two wafers are bonded together. This segmentation allows each process to operate within its optimal temperature range.
Solution Approach 2:
The patent employs three-dimensional stacked integration, bonding the graphene wafer and CMOS wafer together through their oxide layers. This vertical integration approach in the third dimension resolves the temperature incompatibility by allowing independent optimization of each layer's fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the successful integration of graphene into CMOS devices, reducing parasitic capacitance and residual series resistance, thereby enhancing the performance of graphene-based transistors and improving high-frequency functionality.
Implementation Method 1
the first wafer and the second wafer being bonded together by way of an oxide-to-oxide bond between the first and second oxide layers
Data Source
AI summary
Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.