Graphene-Coated Copper Interconnects for Diffusion and Oxidation Control

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Solution Overview

Problem

The reduction in interconnect structure dimensions limits signal propagation speed in semiconductor devices, and the diffusion of copper into dielectric materials affects device reliability, while exposed copper is prone to oxidation during chemical mechanical planarization, shortening the CMP process time.

Innovation Solution

A method involving the formation of a graphene layer on the surface of metal interconnect lines within a semiconductor structure, which prevents metal diffusion into dielectric layers and provides high oxidation resistance, thereby enhancing device reliability and process stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If copper is used as interconnect material to reduce signal propagation delay, then signal propagation speed is improved, but copper diffuses into dielectric material causing device reliability degradation

Engineering Contradiction:
Improvesignal propagation speedVSAvoiddevice reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

A graphene layer is introduced as an intermediary barrier between the copper interconnect line and the dielectric material. This single-atom-thick layer prevents copper diffusion into the dielectric while maintaining electrical conductivity and signal propagation performance, thereby resolving the contradiction between speed and reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The interconnect structure employs a composite material system consisting of copper interconnect lines, graphene barrier layer, and dielectric material. The graphene-copper-dielectric composite prevents copper diffusion while preserving the beneficial electrical properties of copper, achieving both high speed and high reliability

Inventive Principle:
Principle #40Composite materials

2Manufacturing precision

If planarization is performed to expose copper surface, then manufacturing precision is improved, but exposed copper oxidizes rapidly shortening CMP process time

Engineering Contradiction:
Improveplanarization precisionVSAvoidprocess stability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The graphene layer is formed on the copper surface before the CMP planarization process. This preliminary protective action prevents copper oxidation during planarization, maintaining process stability and allowing sufficient CMP process time while achieving the required manufacturing precision

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

Graphene serves as a protective intermediary layer between the copper surface and the oxidizing environment during CMP planarization. It allows precise planarization to be performed while preventing copper oxidation, thus resolving the contradiction between manufacturing precision and process stability

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The graphene layer effectively insulates metal interconnects from dielectric materials, preventing copper diffusion and oxidation, thus improving signal propagation speed and extending the CMP process time, leading to more reliable semiconductor devices.

Implementation Method 1

The graphene layer effectively insulates metal interconnects from dielectric materials, preventing copper diffusion

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Implementation Method 2

provides high oxidation resistance, thereby enhancing device reliability and process stability

Methodology Applied
Scientific EffectOxidation resistance: Oxidation

Data Source

PatentUS11876050B2Method for fabricating interconnection using graphene
Publication Date: 2024.01.16 SEMICON MFG INT (SHANGHAI) CORP
  • US11876050B2 patent drawing
  • US11876050B2 patent drawing
  • US11876050B2 patent drawing

AI summary

Semiconductor fabrication method for manufacturing an interconnect structure is provided. The semiconductor fabrication method for manufacturing an interconnect structure includes providing a substrate structure comprising a substrate, a first dielectric layer on the substrate, and a metal interconnect line extending through the first dielectric layer; removing a portion of the first dielectric layer on the metal interconnect line to form a recess exposing a surface of the metal interconnect line; forming a graphene layer on the exposed surface of the metal interconnect line; and forming a second dielectric layer filling the recess and covering the graphene layer.