Graphene Field Effect Transistor On-Off Ratio via Interlayer Mediator
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Solution Overview
Problem
Graphene-based field effect transistors face challenges in achieving a high on/off ratio due to graphene's zero energy band gap, leading to large off currents and limited integration and speed, despite its excellent charge mobility and thermal conductivity.
Innovation Solution
A field effect transistor design incorporating a graphene channel layer with strategically positioned electrodes and interlayers, including insulation or semiconductor materials, to create a tunnelling effect and modulate the Fermi surface energy level, enhancing the on/off ratio by controlling current flow through voltage applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If graphene is used as a channel layer in field effect transistors, then charge mobility and thermal conductivity are improved, but on/off ratio deteriorates due to zero energy band gap
Solution Approach 1:
The patent introduces an interlayer made of insulating material (such as h-BN, SiO2, or Al2O3) positioned between the graphene channel layer and the second electrode. This interlayer acts as a mediator that enables field effect control of current flow through the graphene while maintaining the electrode separation. The insulating interlayer allows the gate electrode to modulate the Fermi surface energy level of the graphene, thereby controlling the on/off ratio without direct contact between the electrode and graphene channel.
2Ease of manufacture
If graphene is used as a channel layer, then large area integration becomes easier, but off current increases due to semi-metallic properties
Solution Approach 1:
The insulating interlayer serves as a mediator that blocks direct current flow between the graphene channel and the second electrode when the transistor is in the off state. This interlayer prevents the harmful off-current leakage that inherently occurs in semi-metallic graphene, while still allowing field effect control when the transistor is on. The interlayer thickness is controlled to be sufficient to prevent tunneling in the off state but thin enough to allow field penetration for switching control.
3Device complexity
If conventional field effect transistor structures are used with graphene, then fabrication is simplified, but energy band gap control becomes difficult
Solution Approach 1:
The interlayer acts as a controllable mediator that enables energy band gap formation through field effect without requiring complex nanoribbon patterning or chemical composition changes. By applying gate voltage, the Fermi surface energy level of the graphene is modulated, effectively creating an energy barrier that controls current flow. This approach maintains conventional fabrication simplicity while achieving precise energy band gap control through electrical means rather than structural modification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly increases the on/off ratio of the operating current, enabling better integration and high-speed operation of graphene-based transistors, while reducing off-currents and allowing for separate fabrication of n-type and p-type transistors, aligning with CMOS techniques.
Implementation Method 1
the level of the Fermi surface changes by a voltage applied to the gate electrode
Implementation Method 2
a thickness of the interlayer may be sufficient to cause a tunnelling effect between the graphene channel layer and the second electrode
Data Source
AI summary
Provided is a field effect transistor including a graphene channel layer, and capable of increasing an on/off ratio of an operating current by using the graphene of the graphene channel layer. The field effect transistor includes: a substrate; the graphene channel layer which is disposed on a portion of the substrate and includes graphene; a first electrode disposed on a first region of the graphene channel layer and a portion of the substrate; an interlayer disposed on a second region of the graphene channel layer, which is apart from the first region, and a portion of the substrate; a second electrode disposed on the interlayer; a gate insulation layer disposed on a portion of the graphene channel layer, the first electrode, and the second electrode; and a gate electrode disposed on a portion of the gate insulation layer.