Wafer-Scale Graphene Intercalation Doping Under CMOS Thermal Limits
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Solution Overview
Problem
Current methods for doping atomically-thin two-dimensional materials like graphene face challenges in achieving uniform doping over large areas at low temperatures (<450°C) within the thermal budget of CMOS technology, particularly for BEOL applications, due to contamination and defect issues during transfer processes and inefficiencies in conventional doping techniques.
Innovation Solution
An intercalation doping apparatus that applies pressure (2 bar to 500 bar) and temperature (25°C to 500°C) to layered 2D materials, using a reactor chamber with a dopant application system capable of handling solid, liquid, or gaseous dopants, facilitating uniform doping of single or multiple wafers up to 450 mm in diameter, ensuring compatibility with CMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional doping methods are used on transferred graphene, then doping can be achieved, but contamination and defects are introduced during the transfer process
Solution Approach 1:
The graphene is doped during the synthesis process itself, before the transfer step. By incorporating dopant atoms into the graphene lattice while it is being grown on the metal catalyst, the need for post-transfer doping is eliminated, thereby avoiding contamination and defects that would be introduced by handling and transferring the graphene separately
Solution Approach 2:
The doping step is extracted from the post-transfer process and integrated into the synthesis process. Instead of doping after transfer, the dopant is introduced during growth, separating the doping function from the transfer function and eliminating the harmful effects of transfer-related contamination
2Manufacturing precision
If high temperature annealing is applied to achieve uniform doping, then doping uniformity improves, but the process exceeds the CMOS thermal budget
Solution Approach 1:
The doping process is designed to achieve uniform doping at low temperatures by changing the parameters of the synthesis process. By controlling the dopant concentration, gas flow rates, and synthesis temperature within the CMOS thermal budget, uniform doping is achieved without requiring high-temperature annealing that would exceed the thermal budget
Solution Approach 2:
The doping is performed during the synthesis process itself, allowing the dopant to be incorporated uniformly into the graphene lattice as it grows. This preliminary doping action eliminates the need for subsequent high-temperature annealing steps, maintaining compatibility with the CMOS thermal budget
3Ease of manufacture
If transfer steps are used to deposit graphene to the desired substrate, then graphene can be placed on the substrate, but contamination and defects are generated
Solution Approach 1:
The graphene is synthesized directly on the final substrate or on a sacrificial layer that is later removed. By performing the synthesis action preliminarily with the dopant already incorporated, the need for transfer steps is eliminated, avoiding contamination and defects associated with handling and transferring the graphene
Solution Approach 2:
The transfer step is extracted from the manufacturing process entirely. By synthesizing the doped graphene directly on the target substrate or using a removable sacrificial layer, the harmful transfer operation is removed, eliminating the source of contamination and defects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient and uniform doping of large-area substrates, reducing contamination and defect rates, and allowing for high-volume manufacturing of doped graphene interconnects within the strict thermal budget of CMOS technology, enhancing the scalability and reliability of BEOL applications.
Implementation Method 1
intercalation doping involves insertion of the dopant atoms/molecules through the sidewall faces of these materials via diffusion
Implementation Method 2
Sometimes the dopant may require a thermal anneal to move the dopant, for example, Arsenic (As) atoms in monocrystalline Silicon using applied thermal energy to move the As atoms
Implementation Method 3
Acceleration of such doping processes via application of temperature and/or pressure can make the doping process production-capable and inexpensive
Data Source
AI summary
An intercalation doping apparatus including: a reactor chamber where single or multiple wafers or substrates (SoMWoSubs) are disposed within the reactor chamber, where SoMWoSubs have a diameter or a side distance from 25 mm to 450 mm; a heater, where the heater is configured to provide heat to the SOMWoSubs disposed within the reactor chamber, where the SoMWoSubs include a temperature from 25° C. to 500° C.; where pressure is applied to at least one surface of the SOMWoSubs disposed within the reactor chamber within a range of 2 bar to 500 bar; and a dopant application apparatus, where the dopant application apparatus includes at least valves and tubing which bring dopants from outside to within the reactor chamber and includes at least a dopant crucible disposed within the reactor chamber, where the dopants include material in solid, liquid, or gaseous phase, and where the dopants include intercalation doping agents.