Graphene Interconnect Formation Under CMOS Thermal Limits
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Solution Overview
Problem
Existing methods struggle to synthesize high-quality graphene layers over large semiconductor substrates at low temperatures compatible with CMOS technology, as they often damage underlying devices and interconnect layers due to high thermal budgets.
Innovation Solution
A method involving a process chamber with a heatable bottom platen and a movable top platen applies mechanical pressure and temperature to a semiconductor substrate, using a carbon-source material and a metal catalyst layer to form graphene at the interface of the inter-layer dielectric and metal catalyst layer, within a modified commercial bonding tool or pressure-controlled reactor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high temperature processing is used to synthesize graphene layers, then the quality and crystallinity of graphene is improved, but the underlying CMOS devices and interconnects are damaged
Solution Approach 1:
The patent changes the temperature parameter from conventional high-temperature processing (>1000°C) to low-temperature processing (500-900°C) to synthesize graphene. This parameter change allows graphene formation while preserving the integrity of underlying CMOS devices and interconnects that would be damaged at higher temperatures.
Solution Approach 2:
The patent utilizes solid-phase diffusion of carbon atoms through a metal catalyst layer to form graphene. This phase transition process occurs at lower temperatures than conventional methods, enabling graphene synthesis compatible with BEOL processing thermal budgets while avoiding damage to existing devices.
2Manufacturing precision
If conventional high-temperature graphene synthesis methods are used, then high-quality graphene is produced, but the thermal budget for BEOL processing is exceeded
Solution Approach 1:
The patent reduces the processing temperature parameter from conventional >1000°C to 500-900°C, enabling graphene synthesis that fits within the BEOL thermal budget constraints while still producing high-quality graphene with appropriate crystallinity and electrical properties.
3Ease of manufacture
If existing commercial equipment is used without modification, then equipment availability is maintained, but the equipment cannot apply uniform pressure and temperature over large substrate areas
Solution Approach 1:
The patent modifies commercial equipment to include dynamic pressure application capabilities, where pressure is applied uniformly across the entire substrate surface during the diffusion process. This dynamic pressure application, combined with temperature control, enables uniform graphene formation over large substrate areas using adapted commercial equipment.
4Ease of operation
If transfer steps are used to deposit graphene, then graphene can be placed on substrates, but the process becomes cost-ineffective and unfeasible for mainstream electronics
Solution Approach 1:
The patent extracts and eliminates the complex graphene transfer step from the conventional synthesis process. Instead of growing graphene on a separate substrate and transferring it, the method directly synthesizes graphene on the target substrate through solid-phase diffusion, simplifying the process for mainstream electronics manufacturing.
Solution Approach 2:
The patent uses a metal catalyst layer as an intermediary medium that enables direct in-situ graphene formation on the substrate. The carbon source diffuses through this intermediary layer to form graphene directly on the substrate, eliminating the need for separate transfer operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-quality graphene layers on large substrates while adhering to the CMOS thermal budget, avoiding damage to underlying devices and ensuring uniformity and scalability.
Implementation Method 1
Solid-phase diffusion of atoms in a 'material stack' forming a 'diffusion-couple' can be leveraged to synthesize high-quality thin-films
Implementation Method 2
places the semiconductor device substrate on the heatable bottom platen, where the process chamber includes a heatable top platen
Implementation Method 3
the heatable top platen is configured to move up and down to apply a mechanical pressure to the semiconductor device substrate
Data Source
AI summary
A method of forming transistor interconnects on top of a semiconductor device substrate, the method including: providing a semiconductor device substrate with CMOS transistors and an inter-layer dielectric atop the CMOS transistors; depositing a metal (Ni, Co, Ru, or Mo) catalyst layer atop the inter-layer dielectric; depositing a diffusion material including carbon atop the metal catalyst layer; then loading the substrate into a process chamber onto a heatable bottom platen; a heatable top platen applies a mechanical pressure to the substrate; and then forming graphene disposed at an interface of the inter-layer dielectric and the metal catalyst layer, and where the process chamber is a part of a modified or unchanged commercial bonding tool, hot-press tool, or pressure and temperature-controlled reactor.