Graphene Interconnect Structure for Misalignment-Tolerant Contacts

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Solution Overview

Problem

Inadvertent misalignments between conductive features in interconnect structures of integrated circuits lead to increased contact resistance and the risk of short circuits, particularly problematic as technology nodes shrink, affecting device reliability and performance.

Innovation Solution

A graphene layer is formed over conductive features to reduce contact resistance and a selective etch-stop layer is used for proper insulation between conductive features, even when misaligned, ensuring reliable interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conductive features are scaled down to smaller technology nodes, then production efficiency increases and costs decrease, but contact resistance increases due to misalignment between via features and metal line features

Engineering Contradiction:
Improveproduction efficiencyVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

An etch-stop layer is formed over the first conductive feature before the via feature is formed. This preliminary layer ensures that even if misalignment occurs during subsequent processing, the etch-stop layer prevents the via feature from directly contacting adjacent conductive features, thereby preventing short circuits while maintaining the benefits of scaled-down technology nodes

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The etch-stop layer acts as an intermediary element between the via feature and the first conductive feature. This intermediate layer provides a safety margin that accommodates misalignment without causing electrical shorts, thus resolving the contradiction between maintaining small feature sizes for productivity and preventing contact resistance issues for reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If conductive features are scaled down, then geometry size decreases and functional density increases, but the risk of short circuits between uninsulated conductive features increases

Engineering Contradiction:
Improvegeometry sizeVSAvoidshort circuit risk
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The etch-stop layer is formed in advance over the conductive features before the via holes are etched. This preliminary protective layer ensures that even with reduced geometry sizes and tighter spacing, the via features cannot directly short adjacent conductive features, thus enabling continued scaling while mitigating short circuit risks

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The etch-stop layer provides a protective cushion or safety margin before the via feature can reach the conductive feature. This beforehand protection allows the design to tolerate misalignment and maintains insulation between conductive features even at smaller geometry sizes where misalignment has greater impact

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The graphene layer reduces contact resistance and the selective etch-stop layer prevents short circuits, enhancing device reliability and performance by maintaining proper insulation during misalignment.

Implementation Method 1

Graphene-assisted low-resistance interconnect structures and methods of formation thereof

Methodology Applied
Scientific EffectGraphene: Graphene

Implementation Method 2

a selective etch-stop layer is used for proper insulation between conductive features

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Data Source

PatentUS12113021B2Graphene-assisted low-resistance interconnect structures and methods of formation thereof
Publication Date: 2024.10.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12113021B2 patent drawing
  • US12113021B2 patent drawing
  • US12113021B2 patent drawing

AI summary

A semiconductor structure is provided. The semiconductor structure includes a first conductive feature and a second conductive feature disposed in an interlayer dielectric (ILD) layer. The semiconductor structure includes a first graphene layer disposed over the first conductive feature and a second graphene layer disposed over a portion of the second conductive feature. An etch-stop layer (ESL) is horizontally interposed between the first graphene layer and the second graphene layer. A side surface of the first or the second graphene layer directly contacts a side surface of the ESL. A third conductive feature is electrically coupled to the second conductive feature. The third conductive feature is separated from the first graphene layer by a portion of the ESL, and the third conductive feature also directly contacts a top surface of the ESL.